Register Descriptions - Xycom XVME-113 User Manual

3.4

REGISTER DESCRIPTIONS

The functions of the bits in the RTC registers are described in detail in the following sections.
3.4.1
64 Hz Counter (RTC Register 01h)
The 64 Hz Counter Register is a read-only register which can be used to gain access to time values with greater resolution
than one second. The bits in this register will toggle from '0' to '1' at the indicated frequency. For example, the 2 Hz bit
(bit 5) will change from '0' to '1' twice per second.
This register is clocked by an internal 128 Hz source. An internal "carry" occurs each time the 128 Hz clock rolls over,
indicating that the data in the 64 Hz Counter Register is changing. The length of the carry operation is 125 µs. If the
64 Hz Counter Register is being read during this time, the Carry Flag (CF) (bit 7 of Control Register A) will be set to
'1'. The data read during this time is not valid, so the register must be read again. Refer to the procedure for reading the
RTC time in section 3.4.3.
The 64 Hz Counter Register can only be reset using the RESET or 30-sec. ADJ operations. Refer to the description of
these bits in Control Register B in section 3.4.7.3
3.4.2
Seconds, Minutes, Hour Counter Registers (RTC Registers 03h, 05h, 07h)
These registers are used to set or read the RTC time of day using the 24-hour system. Each of the registers is encoded
in BCD format. For example, 59 seconds is expressed in the Seconds Counter Register as '01011001'.
Similar to the 64 Hz Counter Register, an internal carry will occur in the Seconds Counter Register once each second.
The length of the internal carry is 125 µs. If the Seconds Counter Register is being read during this time, the CF (bit
7 of Control Register A) will be set to '1'. The data read during this time is not valid, so the register must be read again.
Refer to the procedure for reading the RTC time in section 3.5.3
None of these registers is affected by RESET. The Seconds Counter and Minutes Counter registers are affected by the
30-sec. ADJ operation. Refer to the description of these bits in Control Register B in section 3.4.7.3
XVME-113 RAM/ROM Memory Module
October 1992
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