Analog Devices CN-0506 Quick Start Manual

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10 Mbps/100 Mbps/1000 Mbps Dual Channel, Low Power Industrial Ethernet PHY

EVALUATION AND DESIGN SUPPORT

Circuit Evaluation Boards
►
CN0506 Circuit Evaluation Board (EVAL-CN0506-FMCZ)
►
Design and Integration Files
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Schematics, Layout Files, Bill of Materials
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CIRCUIT FUNCTIONS AND BENEFITS

The circuit shown in Figure 1 is a dual channel, low latency,
low power Ethernet physical layer (PHY) card that supports 10
Mbps, 100 Mbps, and 1000 Mbps speeds for industrial Ethernet
applications using line and ring network topologies.
Dual channels enable line and ring network topologies that are
commonly used for industrial sensing, control, and distributed con-
trol systems. The Ethernet PHY was extensively tested for electro-
magnetic compatibility (EMC) and electrostatic discharge (ESD)
robustness and supports automatic negotiation to enable linking
with remote PHY devices at the highest common speed advertised.
IEEE 1588 time stamping in the PHY reduces timing uncertainty
Figure 1. EVAL-CN0506-FMCZ Simplified Block Diagram (All Connections and Decoupling Not Shown)
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engineers. Standard engineering practices have been employed in the design and construction of each circuit,
and their function and performance have been tested and verified in a lab environment at room temperature.
However, you are solely responsible for testing the circuit and determining its suitability and applicability for
your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special,
incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any
Circuits from the Lab circuits. (Continued on last page)
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reference designs are engi-
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circuits from Analog Devices have been designed and built by Analog Devices

Devices Connected/Referenced

ADIN1300
Robust, Industrial, Low Latency and Low Power
10 Mbps, 100 Mbps, and 1 Gbps Ethernet PHY
LT3502 1.1 MHz, 500 mA Step-Down Regulator
2
LTC4316 Single I C/SMBus Address Translator
in real-time applications and enhances link loss detection for redun-
dant and real-time applications.
The circuit consists of two individual, independent 10 Mbps, 100
Mbps, and 1000 Mbps PHYs, each with an energy efficient Ethernet
(EEE) PHY core with all the associated common analog circuitry,
input and output clock buffering, management interface, subsystem
registers, media access control (MAC) interface, and control logic.
The design is powered from the host field programmable gate array
(FPGA) mezzanine card (FMC) development board, eliminating the
need for an external power supply. A software programmable clock
enables media independent interface (MII), reduced MII (RMII), and
reduced Gigabit MII (RGMII) MAC interface modes. RJ45 ports with
integrated magnetics keep the solution as compact as possible.
The solution supports cable lengths up to 150 meters at gigabit
speeds and up to 180 meters at 100 Mbps or 10 Mbps.
This solution is typically used in ring or bus topologies. The auto-
matic negotiation feature allows connection with other PHY devices
at the highest supported speed.
Circuit Note
CN-0506
Rev. A | 1 of 6