Pcb Layout - Broadcom AFBR-S50 Reference Design

AFBR-S50 Time-of-Flight (ToF) Sensor Family Application Note
Figure 2: Schematic Reference Design
NOTE: All Gerber files of the AFBR-S50-RD will be available for download on the AFBR-S50 product pages.

2.2 PCB Layout

The PCB layout of the AFBR-S50-RD PCB follows the layout recommendations from the AFBR-S50MV85G data sheet. All
the bypass capacitors are next to the ICs. Only the top layer is populated with components, optimizing both heat dissipation
and manufacturing costs. The AFBR-S50-RD uses four-layer PCB topology, with the two inner layers acting as ground and
power planes (GND and +5V). Most of the signal traces are routed on the bottom layer, allowing high-density PCB design.
A large ground plane ensures low impedance for the signal return paths, therefore eliminating any signal crosstalk. By
shielding the signal traces from the power plane, the ground plane further prevents power supply noise coupling. The
compact size of the entire PCB allows the AFBR-S50-RD to be used as a complete ToF module in an out-of-the-box manner,
cutting the time to market.
The following are the key specifications of the PCB layout:
The PCB uses a four-layer configuration with dedicated ground and power planes.
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Only the top layer is populated to optimize heat dissipation and PCB costs.
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Dimensions of the PCB are 16.5 mm × 18 mm.
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AFBR-S50-RD J1 connector pitch is 1.27 mm (50 mil).
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AFBR-S50 ToF sensor pitch is 1.27 mm (50 mil).
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Broadcom
Reference Design
AFBR-S50-RD-AN100
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