Hardware Documentation - Broadcom AFBR-S50 Reference Design

AFBR-S50 Time-of-Flight (ToF) Sensor Family Application Note

2 Hardware Documentation

This section describes all of the hardware aspects of the AFBR-S50-RD, including the schematics and PCB layout, and it
explains the interconnection between the internal components. It also describes the minimum hardware requirements for the
proper functioning of the AFBR-S50 sensor, including the required speed, memory amount, power supply requirements, and
other parameters that may be of interest to a system integrator.
The following table shows the hardware requirements for using the S50 API and one AFBR-S50 sensor with respect to the
specifications of the MKL17Z256VFM4 (Kinetis KL17Z) MCU from NXP. As the recommended MCU that meets all hardware
requirements, the Kinetis KL17Z is the perfect choice for the AFBR-S50-RD.
NOTE: For more information about the Kinetis KL17Z, see
microcontrollers/arm-microcontrollers/general-purpose-mcus/kl-series-cortex-m0-plus/kinetis-kl1x-48-mhz-
mainstream-small-ultra-low-power-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KL1x.
Note that the memory requirements between the Explorer App and the Example App may vary.
Requirements
CPU core Arm core
CPU frequency 48 MHz
Peripherals SPI Interface with GPIO access
Additional single GPIO IRQ line
2 × GPIO for EEPROM
communication
Lifetime counter
Optional – Periodic interrupt timer
Optional – Nonvolatile memory
interface (for example, Flash)
Memory


Memory used by Kinetis KL17Z in the project build phase (note that the memory requirements may vary).
Memory Explorer App Firmware
Memory Example App Firmware
Broadcom
RAM: 8 KB (4 KB Heap + 4 KB
Stack)
ROM/Flash: 128 KB
Memory Region
PROGRAM_FLASH:
SRAM:
Memory Region
PROGRAM_FLASH:
SRAM:
https://www.nxp.com/products/processors-and-
Kinetis KL17Z Specification
Arm Cortex-M0+ core
48 MHz
Two 16-bit SPI modules supporting up
to 24 Mb/s
28 GPIO pins
Real-time clock
One 6-channel Timer/PWM module
Two 2-channel Timer/PWM modules
One low-power timer
Periodic interrupt timer
256-KB program flash memory
RAM: 32 KB

ROM/Flash: 256KB

Used Size
112472 B
26344 B
Used Size
80780 B
17988 B
Additional Information
Cortex-M0+ or higher Cortex-Mx
processor
API SPI interface is called S2PI
Keeps track of timing in the
magnitude of microseconds
Triggers measurements on a
time-based schedule by using
interrupts
Saves user calibration data upon a
power or reset cycle
Region Size Percentage Used
256 KB 42.90%
32 KB 80.40%
Region Size Percentage Used
256 KB 30.82%
32 KB 54.90%
Reference Design
AFBR-S50-RD-AN100
5