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6.5 Pin Handling
(1) MODE0 and MODE1 pins
When the IE-703002-MC is operated on a stand-alone basis, the MODE0 and MODE1 pins are set to operate in
single mode as follows.
• MODE0: Pull down via 33 kΩ resistor
• MODE1: Pull up via 5.1 kΩ resistor
(2) RESET pin
Pull up via 5.1 kΩ resistor
(3) WAIT pin
Pull up via 5.1 kΩ resistor
(4) CKSEL pin
SW1 in the pod can switch the CKSEL pin between a pull-up/pull-down resistor.
(5) PLLSEL pin (V852)
SW2 in the pod can switch the PLLSEL pin between a pull-up/pull-down resistor.
CHAPTER 6 CAUTIONS
Figure 6-1. Circuit Diagram of PLLSEL Pin and CKSEL Pin
V852 PLLSEL pin
3 V
100 Ω
SW1
220 Ω
33 kΩ
GREEN
3 V
100 Ω
SW2
220 Ω
33 kΩ
GREEN
V852
CKSEL pin
User's Manual U11595EJ5V0UM
PLLSEL
Emulation
CPU
CKSEL
47
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