Chip-Set; Bridge Chip (Sis5581) - HP Vectra VE5 4 Technical Reference Manual

PL Bus Interface
PCI Bus Interface
ISA Bus Interface
2 System Board

Chip-Set

Chip-Set
The chip-set comprises two chips. These interface between the three main
buses (the Processor-Local bus, the PCI bus and the ISA bus).
• The Bridge chip (SiS5581) is a combined PL/PCI bridge and cache
controller and main memory controller and PCI/ISA bridge and IDE
controller and USB controller.
• The Super I/O chip (NS87317) is a combined serial interface and paral-
lel interface and keyboard controller and mouse controller and flexible
disk drive controller.

Bridge Chip (SiS5581)

The bridges between the Processor Local Bus (PL Bus) and the PCI Bus,
and between the PCI Bus and the ISA Bus, are encapsulated in a 553-pin ball
grid array (BGA) package.
The chip monitors each cycle that is initiated by the processor, and forwards
those to the PCI bus that are not targeted at the local memory. It translates
PL bus cycles into PCI bus cycles.
The chip supports the SMM mode of the Pentium processor, the CPU stop
clock hardware function, and the keyboard lock function.
The chip-set is PCI 2.1 compliant, and provides for PCI Concurrency.
Concurrent data transfers that do not contest for the same resources (such
as processor to memory concurrent with PCI peer to peer, or processor to
ISA device concurrent with PCI device to memory) are allowed to interleave
their transfers.
The PCI arbiter supports PCI bus arbitration for up to four masters using a
rotating priority mechanism. Its hidden arbitration scheme minimizes
arbitration overhead.
As well as accepting cycles from the PCI bus interface, and translating them
for the ISA bus, the ISA bus interface also requests the PCI master bridge to
generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface
contains a standard ISA bus controller and data buffering logic, and can
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