HP Vectra VE5 4 Technical Reference Manual page 23

Flash program enable (FLASHLOCK)
Backplane ID0 (always 1)
Backplane ID1 (always 1)
Bus core frequency BCF0 (connected to SW-3, open=1, closed=0)
Bus core frequency BCF1 (connected to SW-4, open=1, closed=0)
Host bus request detect (60/66 MHz) (connected to SW-1, always 0)
Serial EEPROM data
FDD write protect (not used)
Password enable (connected to SW-7, open=1, closed=0)
Clear CMOS (connected to SW-8, open=1, closed=0)
Serial EEPROM chip select
Serial EEPROM clock
Description
2 System Board
Chip-Set
GPIO number
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
23