Chip-Set - HP Vectra VE5 3 Series Technical Reference Manual

Chip-Set

The chip-set comprises three chips, each encapsulated in a 208 pin plastic
quad flat pack (PQFP) package.
The PCMC chip (SiS 5511) is a combined PL/PCI bridge and cache
controller and main memory controller and PCI arbiter.
The PLDB chip (SiS 5512) provides the PCI local data buffer and PCI-to-
Processor-Local bus data path.
The PSIO chip (SiS 5513) provides the PCI/ISA bridge, responsible for
transferring data between the PCI bus and the ISA expansion bus, and also
contains the 2-channel IDE controller.
Chip
SiS 5511 • Asynchronously clocked PCI bus support
• VGA unified memory architecture support (with DMA)
• PCI arbiter
• Main memory controller (EDO), 32-bit/64-bit mixed mode
• Level-2 cache memory controller (write through and write back modes)
SiS 5512 • Bidirectional buffering (64 bit PL bus, 64/32-bit memory data bus, 32-bit PCI bus)
• Three FIFO queues, and one read buffer
SiS 5513 • PCI to ISA, and ISA to PCI bus cycle translation
• PCI master/slave IDE controller (supporting 4 devices, 2 on each of 2 channels)
• 7-channel programmable DMA controller
• 16-level programmable interrupt controller
• Programmable timer with 3 counters
• Real time clock (RTC) with 256 bytes of CMOS SRAM (not used)
• Plug-and-Play
Devices on the Processor-Local Bus
Features
2 System Board
15