HP Vectra VE5 3 Series Technical Reference Manual page 57

Test
LED Test
System (BIOS) ROM Test
RAM Refresh Timer Test
Interrupt RAM Test
Shadow the System ROM
BIOS
Load CMOS Memory
CMOS RAM Test
CPU Cache Memory Test
Initialize the Video
8042 Self-Test
Timer 0/Timer 2 Test
DMA Subsystem Test
Interrupt Controller Test
Real-Time Clock Test
RAM Address Line
Independence Test
Size Extended Memory
5 Power-On Self-Test and Error Messages
Description
System BIOS Tests
Tests the LEDs on the control panel.
Calculates an 8-bit checksum. Test failure causes the boot process to
abort.
Tests the RAM refresh timer circuitry. Test failure causes the boot process
to abort.
Checks the first 64 KB of system RAM used to store data corresponding to
various system interrupt vector addresses. Test failures cause the boot
process to abort.
Tests the system ROM BIOS and shadows it. Failure to shadow the ROM
BIOS will cause an error code to display. The boot process will continue,
but the system will execute from ROM. This test is not performed after a
soft reset (using
Checks the serial EEPROM and returns an error code if it has been
corrupted. Copies the contents of the EEPROM into CMOS RAM.
Checks the CMOS RAM for start-up power loss, verifies the CMOS RAM
checksum(s). Test failure causes error codes to display.
Tests the processor's internal level-one cache RAM. Test failure causes an
error code to display and the boot process to abort.
Video Tests
Initializes the video subsystem, tests the video shadow RAM, and, if
required, shadows the video BIOS. A failure causes an error code to
display, but the boot process continues.
System Board Tests
Downloads the 8042 and invokes the 8042 internal self-test. A failure
causes an error code to display.
Tests Timer 0 and Timer 2. Test failure causes an error code to display.
Checks the DMA controller registers. Test failure causes an error code to
display.
Tests the Interrupt masks, the master controller interrupt path (by forcing
an IRQ0), and the industry-standard slave controller (by forcing an IRQ8).
Test failure causes an error code to display.
Checks the real-time clock registers and performs a test that ensures that
the clock is running. Test failure causes an error code to display.
Memory Tests
Verifies the address independence of real-mode RAM (no address lines
stuck together). Test failure causes an error code to display.
Sizes and clears the protected mode (extended) memory and writes the
value into CMOS bytes 30h and 31h. If the system fails to switch to
protected mode, an error code is displayed.
Order in Which Tests are Performed
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