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Port
Pin Terminals I/O
PA
15
68
14
67
13
66
12
65
11
64
10
62
9
61
8
60
7
58
6
57
5
56
4
55
3
54
2
53
1
52
0
51
PB
15
100
14
99
13
98
12
97
11
96
10
95
9
94
8
93
7
91
6
90
5
89
4
87
3
86
2
85
1
84
0
83
8.2. IC2 (ASIC)
ACT
I
nIRQ3
L
I
nIRQ2
L
nIRQ1
I
L
nIRQ0
I
L
PA11
O
L
PA10
I
L
PA9
-
-
nBREQ
I
L
nBACK
O
L
nRD
O
L
nLBS
O
L
nWR
O
L
nWAIT
O
L
nCS6
O
L
PA1
-
-
PA0
-
-
nIRQ7
-
-
nIRQ6
-
-
nIRQ5
I
L
nIRQ4
I
L
PB11
-
-
PB10
-
-
TxD0
O
H/L UART port to send data [TxD0] (RS232C)
RxD0
I
H/L UART port to receive data [RxD0] (RS232C)
PB7
-
-
PB6
-
-
PB5
I
L
PB4
I
L
PB3
I
L
PB2
I
L
PB1
I
L
PB0
I
H
Reserve (interrupt)
T1_IC(IC302) interrupt
Interrupt for SAMSON (ASIC) (mainly DPRAM communication
interrupt for MPR)
DC power down recovery detection inversion signal of
(IC1) inversion signal (L:recovery)
UART port for request to send [RTS0] (RS232C)
UART port for clear to send [CTS0] (RS232C)
Reserve (general-purpose i/o)
Bus request signal (bus arbitration)
Bus acknowledge signal (bus arbitration)
Read signal (bus control)
Low byte strobe signal (bus control)
Write signal(bus control)
Wait signal(bus control)
Chip select 6 signal(bus control)
Reserve (Chip Select 5 signal)
Reserve (Chip Select 4 signal)
Reserve (interrupt)
Reserve (interrupt)
Line Reception Multi-frame Boundary Signal Input (nRxMF)
Line Reference Lost Interruption, or Polling by i/o Setting
Reserve (general-purpose i/o)
Reserve (general-purpose i/o)
Reserve (general-purpose i/o)
Reserve (general-purpose i/o)
For manufacturing test L:Manufacturing test mode
For card single debugging L:debug mode
Flash memory busy input (L:busy)
Reserve (general-purpose i/o)
Reserve (general-purpose i/o)
CPU (IC1) inversion signal (H:inversion)
30
Description
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