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7.1.2. Chip Select Logic
Table.5.2 Table of Chip Select Terminals
Terminals
CS
Individual
Terminals
Output (1)
nCS0 (area
-
0)
nCS1 (area
nCASH
1)
(DRAM)
nCS2 (area
-
2)
nCS3 (area
nCASL
3)
(DRAM)
nCS4 (area
PA0 (I/O)
4)
nCS5 (area
PA1 (I/O)
5)
nCS6 (area
PA2 (I/O)
6)
nCS7 (area
PA3 (I/O)
7)
Table.5.3 Table of Chip Select Port allocation
Chip Select
Address
nCS0
0000000h
l
0FFFFFFh
nCS1
1000000h
l
1FFFFFFh
nCS2
A000000h
l
AFFFFFFh
nCS6
6000000h
l
6FFFFFFh
Function
used
Individual
Output (2)
-
nCS0
-
nCS1
-
nCS2
-
nCS3
TIOCA0
nCS4
(Timer)
nRAS (DRAM)
nCS5
TIOCB0
nCS6
(Timer)
nWAIT
nWAIT
Device Bit
Assignment
Wide
Device
16bit
Flash
(IC5)
8bit
ASIC
(IC2)
16bit
SRAM
(IC3)
8bit
T1_IC
(IC302)
18
Wait Function
(Numeral is no. of
clocks.)
1+Programable or 1+
Programable+WAIT
Terminals
Read 1/Write 2 or 2+
WAIT Terminals
1+Programable or 1+
Programable+WAIT
Terminals
Read 1/Write 2 or 2+
WAIT Terminals
Read 1/Write 2 or 2+
WAIT Terminals
Read 1/Write 2 or 2+
WAIT Terminals
1+Programable or 1+
Programable+WAIT
Terminals
Read 1/Write 2 or 2+
WAIT Terminals
Bus Cycle
2 Clock (1+Long
Port allocation of word by
Wait1)
static bus sizing Bus cycle
has same setting as Area
(nCS2).
2+WAIT Terminals Port allocation of byte by
static bus sizing.
2 Clock (1+Long
Port allocation of word by
Wait1)
static bus sizing Bus cycle
has same setting as Area
(nCS0).
3 Clock (1+Long
Port allocation of byte by
Wait2)
static bus sizing.
Remarks
Used for Flash memory
Used for ASIC (IC2)
Used for SRAM (Basic)
Work Area
CS Reserve
CS Reserve
CS Reserve
Used for peripheral
Used for framer IC,
CS.
Used for Input Wait
Terminals.
Remarks
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