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(The configuration with the interruption processing is to give a
consistency with the existing PBX.)
- Since the nRxMF signal of the T1-IC (IC302) occurs in periodic
frame timing, the polling by i/o port is impossible.
7.2. LINE INTERFACE FUNCTION
7.2.1. Line Interface Outline
T1 card uses the T1-IC (IC302)(Mitel) as the IC for the line interface. Fig. 5.2 shows the outline
block diagram of the T1-IC (IC302) and Fig. 5.2 shows the characteristics of the T1-IC (IC302).
Also, see the T1-IC (IC302) Data Sheet for the detailed specifications.
Table.5.4 Characteristics of the T1-IC (IC302)
Item
Line Extraction Clock
DPLL
Elastic Buffer
Signaling Controller
FIFO (HDLC0)
FIFO (HDLC1)
PCM Highway Interface ST-BUS Interface (2.048Mbps)
P-Interface
Fig.5.2 Outline block diagram of the T1-IC (IC302)
Contents
1.544MHz
Low Jitter DPLL for clk generation
Two-frame elastic buffer (Rx & Tx)
-
HDLC0: ESF Data Link
(4kbps)
-
HDLC1: DS1 Channel24
(56 or 64kbps)
128Byte x 2
128Byte x 2
8bit parallel Bus (Intel/Motorola)
Built-in two pieces
TX/RX Variable in the range from 16 Byte
to 128Byte in increments of 16Byte.
TX/RX Variable in the range from 16 Byte
to 128Byte in increments of 16Byte.
Used Intel Mode for T1 Card.
20
Remarks
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