Uart; Adc; Strapping Pins - Espressif Systems ESP32-C3FH4 Hardware Design Manuallines

2 Schematic Checklist
VDD33
2.5 RF
C
In your circuit design, please add a π-matching network for antenna matching, preferably a CLC network.
GND
ANT1
PCB_ANT
B
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.

2.6 UART

You need to connect a 499 Ω resistor to the U0TXD line to suppress the 80 MHz harmonics.

2.7 ADC

It is recommended to add a 0.1 µF filter capacitor between pins and ground when using the ADC function. A
Please note that ADC2 is not factory-calibrated. We recommend using ADC1.

2.8 Strapping Pins

Note:
The content below is excerpted from Section Strapping Pins in
ESP32-C3 family has three strapping pins:
• GPIO2
• GPIO8
• GPIO9
Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference
During the chip's system reset, the latches of the strapping pins sample the voltage level as strapping bits of "0"
or "1", and hold these bits until the chip is powered down or shut down.
Types of system reset include:
Espressif Systems
C3
1uF
GND
L1 2.0nH
C5 C6
10uF 0.1uF
GND
RF_ANT
TBD
1 L2
2
C8
TBD TBD
GND GND
The values of C8, L2 and C9
vary with the actual PCB board.
 ‘ …‘’‘‡–
Figure 9: ESP32­C3 Family RF Matching Schematic
5
Manual.
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C4
100pF
GND
GND
C7
0.1uF
GND
LNA_IN
1
2
3
C9
GPIO0 4
GPIO1 5
GPIO2 6
CHIP_EN
7
GND
GPIO3 8
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
ESP32-C3 Family Datasheet.
11
ESP32-C3 Family Hardware Design Guidelines V1.0
LNA_IN
VDD3P3
VDD3P3
XTAL_32K_P
XTAL_32K_N
GPIO2
CHIP_EN
GPIO3
U2
4
R
24 R
SPIQ
23 R
SPID
22
R
SPICLK
21
SPICS0
20 R
SPIWP
19
R
SPIHD
18
VDD_SPI
17
VDD3P3_CPU
G
ESP32-C3
G