Espressif Systems ESP32-C3FH4 Hardware Design Manuallines page 23

3 PCB Layout Design
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace
should be routed at a 135° angle, or with circular arcs if trace bends are required.
• Please place the π-matching network in a zigzag. For 0201 package, please add a stub between the
ground and the two capacitors in parallel to curb second harmonics. It is preferable to keep the stub length
15 mil, and determine the stub width according to the number of PCB layers, so that the characteristic
impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to the third layer, and
maintain a keep-out area on the first and second layers. If space on PCB is limited, you may add the stub
only to parallel capacitors near the chip. The trace highlighted in Figure
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR, high-frequency clocks, etc. In
addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded
by ground copper and ground vias .
• For designing the RF trace at 50 Ω single-ended impedance, please refer to the PCB stack-up design
shown in Figure 20.
Espressif Systems
Figure 19: ESP32­C3 RF Stub in a Four­layer PCB Design
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ESP32-C3 Family Hardware Design Guidelines V1.0
is the stub.