Texas Instruments TMS320F2807 Series Manual page 3

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4 Usage Notes and Known Design Exceptions to Functional Specifications
4.1 Usage Notes
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
Table 2 shows which silicon revision(s) are affected by each usage note.
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
Caution While Using Nested Interrupts
SYS/BIOS: Version Implemented in Device ROM is not Maintained
SDFM: Use Caution While Using SDFM Under Noisy Conditions
4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt
Mask Clear
Revision(s) Affected: B, C
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state
that can trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other
interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it
happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be
triggered after the nested interrupt reenables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is
shown below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF;
EINT;
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF;
asm(" NOP");
EINT;
4.1.2 Caution While Using Nested Interrupts
Revision(s) Affected: B, C
If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order
to use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so
may cause undefined behavior of CPU execution.
SPRZ423H – October 2014 – Revised February 2020
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Usage Notes and Known Design Exceptions to Functional Specifications
Table 2. List of Usage Notes
TITLE
//Enable nesting in the PIE
//Enable nesting in the CPU
//Enable nesting in the PIE
//Wait for PIEACK to exit the pipeline
//Enable nesting in the CPU
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SILICON REVISION(S)
TMS320F2807x MCUs Silicon Revisions C, B
AFFECTED
B C
Yes Yes
Yes Yes
Yes Yes
Yes Yes
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