Texas Instruments TMS320F2807 Series Manual page 11

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Advisory
ADC: DMA Read of Stale Result
B, C
Revision(s) Affected
The ADCINT flag can be set before the ADCRESULT value is latched (see the t
Details
t
INT(LATE)
Manual). The DMA can read the ADCRESULT value as soon as 3 cycles after the
ADCINT trigger is set. As a result, the DMA could read a prior ADCRESULT value when
the user expects the latest result if all of the following are true:
•
•
•
•
•
Only the DMA reads listed above could result in reads of stale data; the following non-
DMA methods will always read the expected data:
•
•
•
Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy
Workaround(s)
transaction. This will result in enough delay that the second channel will always read the
fresh ADC result.
Advisory
ADC: Random Conversion Errors
B
Revision(s) Affected
The ADC may have errors at a rate as high as 1 in 10
Details
conversion error occurs, it will be a significant random jump in the digital output of the
ADC without a corresponding change in the ADC input voltage, otherwise known as a
"sparkle code". The magnitude of this jump will typically be in the range of 20 LSBs to
200 LSBs; however, larger or smaller jumps may occur.
For the revisions affected, the error rate will be lower than 1 error in 10
Workaround(s)
conversions when all of the following configurations are used:
•
•
•
•
Advisory
ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule
B
Revision(s) Affected
The ADCxEVT trigger to the ePWM digital compare submodule may not be detected by
Details
the ePWM.
The ADCxEVT can generate an ADCx_EVT interrupt to the PIE. The ISR can be used to
Workaround(s)
perform the desired task in software.
SPRZ423H – October 2014 – Revised February 2020
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Usage Notes and Known Design Exceptions to Functional Specifications
columns in the ADC Timings table of the
The ADC is in late interrupt mode.
The ADC operates in a mode where t
(ADCCTL2 [PRESCALE] > 2 for 12-bit mode).
The DMA is triggered from the ADCINT signal.
The DMA immediately reads the ADCRESULT value associated with that ADCINT
signal without reading any other values first.
The DMA was idle when it received the ADCINT trigger.
The ADCINT flag triggers a CLA task.
The ADCINT flag triggers a CPU ISR.
The CPU polls the ADCINT flag.
The S+H duration is at least 320 ns
ADCCLK is 40 MHz or less
ADCCLK prescale is a whole number: /1.0, /2.0, /3.0, /4.0, /5.0, /6.0, /7.0, or /8.0
The value of 0x7000 is written to memory locations 0x0000 743F, 0x0000 74BF,
0x0000 753F, and 0x0000 75BF (writing this value is only valid when the ADCCLK
prescale is a whole number).
Copyright © 2014–2020, Texas Instruments Incorporated
TMS320F2807x Microcontrollers Data
occurs 3 or more cycles before t
INT(LATE)
6.5
ADC conversions. When a
TMS320F2807x MCUs Silicon Revisions C, B
and
LAT
LAT
14.5
ADC
11