JVC XV-521BK Service Manual page 46

XV-521BK/523GD/522SL
Symbol
I/O
Pin No.
44 PIO28
I/O
PIO29
45
46 PIO30
-
VDD-3.3
47
I/O
PIO31
48
-
49 VSS
O
NC
50
51
52
I/O
PIO1
53
MDATA15 I/O
54
I/O
MDATA0
55
-
VDD-3.3
56
MDATA14 I/O
57
-
VSS
58
MDATA1
59
I/O
MDATA13
60
MDATA2
61
VDD-3.3 -
62
I/O
MDATA12
63
VSS -
64
I/O
MDATA3
65
-
VDD-2.5
66
MDATA11 I/O
67
-
VSS
68
MDATA4 I/O
69
-
VDD-3.3
70
I/O
MDATA10
71
VSS -
72
MDATA5
73
MDATA9 I/O
74
MDATA6
75
-
VDD-3.3
76
MDATA8 I/O
77
-
VSS
78
MDATA7 I/O
79
O
LDQM
80
O
UDQM
81
VDD-3.3 -
82
O
MWE
83
-
VSS
84
O
SD-CLK
85
SD-CAS O
86
O
SD-RAS
87
VDD-3.3 -
88
O
SD-CS1
89
-
VSS
90
O
SD-CS0
91
-
VDD-2.5
92
NC O
93
-
VSS
94
O
NC
95
-
VDD-3.3
96
O
MADDR9
97
VSS -
98
O
MADDR11
1-46
Function
Programmable I/O pins. Output mode after reset
3.3-V supply voltage for I/O signals.
Programmable I/O pins. Output mode after reset
Ground for core logic and I/O signals.
No Connection
Programmable I/O pins. Input mode after reset
Memory data
Memory data
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
2.5-V supply voltage for core logic.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for I/O signals.
SDRAM write enable. Decoder asserts active LOW to request a write operation to the
SDRAM array.
Ground for core logic and I/O signals.
SDRAM system clock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for I/o signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
2.5-V supply voltage for core logic.
No Connection.
Ground for core logic and I/O signals.
No Connection.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
ZIVA3-PEO (2/5)