JVC XV-521BK Service Manual page 35

Symbol
Pin NO.
46 CPUADR10
47 CPUADR9
48 CPUADR8
49 CPUADR7
50 CPUADR6
51 CPUADR5
52 CPUADR4
53 CPUADR3
54 CPUADR2
55 CPUADR1
56 VSS
57 CPUADR0
58 NCS
59 NWR
60 NRD
61 VDD
62 CPUDT7
63 CPUDT6
64 PVPPDRAM
65 PTESTDRAM
66 PVDDDRAM
67 PVSSDRAM
68 CPUDT5
69 CPUDT4
70 CPUDT3
71 VSS
72 CPUDT2
73 CPUDT1
74 CPUDT0
75 CLKOUT1
76 VDD
77 TEHLD
78 DTRD
79 IDGT
80 BDO
81 CPDET2
82 CPDET1
83 VSS
84 MMOD
85 NRST
86 VDD
87 CLKOUT2
88 SBCK/PLLOK
89 IDOHOLD
90 JMPINH
Function
I/O
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
GND
-
System control address
I
System control chip selec
I
System control write
I
System control read
I
Apply 3V
-
System control data
I/O
System control data
I/O
VSS connected
O
VSS connected
I
VDD (2.7V) connected
VSS connected
System control data
I/O
System control data
I/O
System control data
I/O
GND
-
System control data
I/O
System control data
I/O
System control data
I/O
16.9/11.2/8.45MHz clock
O
Apply 3V
-
Mirror gate (Connect to TP141)
O
Data part frequency control switch (Connect to TP304)
O
Part CAPA switch (Connect to TP305)
O
RF dropout / BCA data of making to binary
I
Outer side CAPA detection
I
Side of surroundings on inside
I
GND
-
VSS connected
I
System reset
I
Apply 3V
-
16.9MHz clock
O
Frame mark detection
O
ID gate for tracking holding (Connect to TP307)
O
Jump prohibition
O
XV-521BK/523GD/522SL
1-35