JVC XV-521BK Service Manual page 32

XV-521BK/523GD/522SL
2.Pin function
Symbol
I/O
Pin No.
1
I
WAIT
2
RE O
3
O
SPMUTE
4
WEN O
5
CS0 O
6
O
CS1
7
CS2 O
8
O
CS3
9
DRVMUTE O
10
SPKICK O
11
O
LSIRST
12
WORD O
13
O
A0
14
A1 O
15
A2 O
16
O
A3
17
VDD -
18
O
SYSCLK
19
VSS -
20
XI -
21
-
XO
22
VDD -
23
I
OSCI
24
OSCO O
25
I
MODE
26
O
A4
27
A5 O
28
O
A6
29
A7 O
30
O
A8
31
O
A9
32
A10 O
33
O
A11
34
VDD -
35
O
A12
36
O
A13
37
A14 O
38
O
A15
39
A16 O
40
O
A17
41
O
A18
42
A19 O
43
-
VSS
44
A20 O
45
O
TXSEL
46
O
HAGUP
47
/ADPD
48
O
CD/DVD
49
HMFON
50
I
TRVSW
1-32
Function
Micon wait signal input
Read enable
Write enable
Non connect
Chip select for ODC
Chip select for ZIVA
Chip select for outer ROM
Driver mute
Spin kick (Non connect)
LSI reset
Bus selection input
Address bus 0 for CPU
Address bus 1 for CPU
Address bus 2 for CPU
Address bus 3 for CPU
Power supply
System clock signal output
Ground
Not use (Connect to vss)
Non connect
Power supply
Clock signal input(13.5MHz)
Clock signal output(13.5MHz)
CPU Mode selection input
Address bus 4 for CPU
Address bus 5 for CPU
Address bus 6 for CPU
Address bus 7 for CPU
Address bus 8 for CPU
Address bus 9 for CPU
Address bus 10 for CPU
Address bus 11 for CPU
Power supply
Address bus 12 for CPU
Address bus 13 for CPU
Address bus 14 for CPU
Address bus 15 for CPU
Address bus 16 for CPU
Address bus 17 for CPU
Address bus 18 for CPU
Address bus 19 for CPU
Ground
Address bus 20 for CPU
TX Select
Detection switch of traverse
inside
Symbol
I/O
Pin No.
I
51 FGIN
52 TRS
O
53 ADSCEN
54 VDD -
55 FEPEN O
O
56 SLEEP
57 BUSY I
O
58 REQ
59 CIRCEN O
60 HSSEEK O
-
61 VSS
62 EPCS O
O
63 EPSK
64 DPDI I
65 EPDO O
-
66 VDD
67 SCLKO I
I
68 S2UDT
69 U2SDT O
70 CPSCK O
I
71 SDIN
72 SDOUT O
-
73 -
74 - -
75 NMI -
I
76 ADSCIRQ
77 ODCIRQ I
I
78 DECIRQ
79 WAKEUP O
I
80 ODCIRQ2
I
81 ADSEP
82 RST I
-
83 VDD
84 TEST1 I
I
85 TEST2
I
86 TEST3
87 TEST4 I
I
88 TEST5
89 TEST6 I
I
90 TEST7
I
91 TEST8
92 VSS -
I/O
93 D0
94 D1 I/O
I/O
95 D2
I/O
96 D3
97 D4 I/O
I/O
98 D5
99 D6 I/O
I/O
100 D7
Function
Photo input
Serial enable signal for ADSC
Power supply
Serial enable signal for FEP
Standby signal for FEP
Communication busy
Communication Request
CIRC command select
Seek select
Ground
EEPROM chip select
EEPROM clock
EEPROM data input
EEPROM data output
Power supply
Communication clock
Communication input data
Communication output data
Clock for ADSC serial
ADSC serial data input
ADSC serial data output
Not use
Not use
Not use
Interrupt input of ADSC
Interrupt input of ODC
Interrupt input of ZIVA
Not use
Address data selection input
Reset input
Power supply
Test signal 1 input
Test signal 2 input
Test signal 3 input
Test signal 4 input
Test signal 5 input
Test signal 6 input
Test signal 7 input
Test signal 8 input
Ground
Data bus 0 of CPU
Data bus 1 of CPU
Data bus 2 of CPU
Data bus 3 of CPU
Data bus 4 of CPU
Data bus 5 of CPU
Data bus 6 of CPU
Data bus 7 of CPU