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Table 5.5 Timing requirements and switching characteristics (Vcc = 3.0 V, Ø = 6 MHz)
Symbol
td (ø-AH)
AB15 - AB8 delay time
tv (ø-AH)
AB15 - AB8 valid time
td (ø-AL)
AB7 - AB0 delay time
tv (ø-AL)
AB7 - AB0 valid time
td (ø-WR)
WR* delay time
tv (ø-WR)
WR* valid time
td (ø-RD)
RD* delay time
tv (ø-RD)
RD* valid time
td (ø-DMA)
DMAOUT delay time
tv (ø-DMA)
DMAOUT valid time
tsu (RDY-ø)
RDY setup time
th (ø-RDY)
RDY hold time
tsu (HOLD-ø)
HOLD* setup time
th (ø-HOLD)
HOLD* hold time
td (ø-HLDAL)
HLDA* "L" delay time
td (ø-HLDAH) HLDA* "H" delay time
tsu (DB-ø)
Data bus setup time
th (ø-DB)
Data bus hold time
td (ø-DB)
Data bus delay time
tv (ø-DB)
Data bus valid time
td (ø-EDMA)
EDMA* delay time
tv (ø-EDMA)
EDMA* valid time
td (AH-WR)
Before WR* AB15 - AB8 valid time
td (AL-WR)
Before WR* AB7 - AB0 valid time
tv (WR-AH)
After WR* AB15 - AB8 valid time
tv (WR-AL)
After WR* AB7 - AB0 valid time
td (AH-RD)
Before RD* AB15 - AB8 valid time
td (AL-RD)
Before RD* AB7 - AB0 valid time
tv (RD-AH)
After RD* AB15 - AB8 valid time
tv (RD-AL)
After RD* AB7 - AB0 valid time
tsu (RDY-WR) Before WR* RDY setup time
th (WR-RDY)
After WR* RDY hold time
tsu (RDY-RD) Before RD* RDY setup time
th (RD-RDY)
After RD* RDY hold time
tsu (DB-RD)
Before RD* data bus setup time
th (RD-DB)
After RD* data bus hold time
td (WR-DB)
Before WR* data bus delay time
tv (WR-DB)
After WR* data bus valid time
tv (WR-EDMA) After WR* EDMA* delay time
tv (RD-EDMA) After RD* EDMA* delay time
Item
Min.
35
21
15
0.5*tc(ø)-33
0.5*tc(ø)-35
0.5*tc(ø)-33
0.5*tc(ø)-35
45
45
18
12
( 52 / 68 )
Standard value
Actual MCU
Emulator
Max.
Min.
45
0
-4
47
0
-4
8
0
0
8
0
0
26
0
-4
68
0
0
34
0
0
30
30
9
49
0
0
30
8
15
0
0
0.5*tc(ø)-34
0.5*tc(ø)-35
0
-5
0
-5
0.5*tc(ø)-41
0.5*tc(ø)-43
0
-5
0
-5
83
0
0
76
0
0
56
0
0
28
3
0
0
0
0
Unit
Max.
51
ns
ns
52
ns
ns
15
ns
ns
15
ns
ns
32
ns
ns
ns
ns
ns
ns
30
ns
30
ns
ns
ns
36
ns
ns
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29
ns
ns
ns
ns
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