Renesas M3A-HS49 User Manual page 48

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Table3.2.6 lists functions of switch SW4. SH7149 operating mode is determined by the setting of the MD0, MD1 and
FWE pins. Table3.2.7 lists the selection of SH7149 operating modes.
No. Setting
SW4-1 OFF
FWE
ON
SW4-2 OFF
MD1 ON
SW4-3 OFF
MD0
ON
: Initial Setting
SW4-1 SW4-2
(FWE) (MD1)
ON ON
ON ON
ON OFF
ON OFF
OFF ON
OFF ON
OFF OFF
OFF OFF
: Initial Setting
Table3.2.8 lists functions of LEDs mounted in M3A-HS49.
No. Color
LED1 Blue
LED2 Green
LED3 Green
LED4 Green
LED5 Green
LED6 Green
LED7 Green
Red
LED8
Yellowgreen
Rev.1.0 Dec 15, 2006
REJ10J0917-0100
Table3.2.6 Functions of Switch SW4
FWE=H (Releasing the writing/erasing protects of on-chip flash memory)
FWE=L (Setting the writing erasing protects of on-chip flash memory)
MD1 pin state "H"
MD1 pin state "L"
MD0 pin state "H"
MD0 pin state "L"
Table3.2.7 Selection of SH7149 operating modes
SW4-3
(MD0)
Operating mode
ON Mode0
OFF Mode1
ON Mode2
OFF Mode3
ON Mode4
OFF Mode5
ON Mode6
OFF Mode7
Table3.2.8 Functions of LEDs Mounted in M3A-HS49
Power-on LED (LED1 lights when power is supplied)
Open to the user (LED2 lights when PE0 outputs "L")
Open to the user (LED3 lights when PE9 outputs "L")
Open to the user (LED4 lights when PE11 outputs "L")
Open to the user (LED5 lights when PE12 outputs "L")
Open to the user (LED6 lights when PE14 outputs "L")
Open to the user (LED7 lights when PE15 outputs "L")
Interrupt confirmation (LED8 lights red when pushing at NMI switch (SW5).
Interrupt confirmation (LED8 lights yellowgreen when pushing IRQ0 switch (SW6).
Function
SH7149 Operating mode
Mode name
MCU extension mode0
(On-chip ROM not active, CSO space: 8-bit bus width)
MCU extension mode1
(On-chip ROM not active, CSO space: 8-bit bus width))
MCU extension mode2 (On-chip ROM active)
Single chip mode (On-chip ROM active)
Boot mode (On-chip ROM active)
User Boot mode (On-chip ROM active)
User Programming mode (On-chip ROM active)
User Programming mode (On-chip ROM active)
Functions/Remarks
Operational Specifications
3.2.4 Switch and LED Functions
CPU mode setting
(ref. Table3.2.7)
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