NXP Semiconductors ADC1412D Series Quick Start Manual
  1. Manuals
  2. Brands
  3. NXP Semiconductors Manuals
  4. Motherboard
  5. ADC1412D Series
  6. Quick start manual
NXP Semiconductors ADC1412D Series Quick Start Manual

NXP Semiconductors ADC1412D Series Quick Start Manual

Hide thumbs Also See for ADC1412D Series:
Table of Contents

Advertisement

Quick Links

Download this manual
Quick start ADC1412D,
ADC1212D, ADC1112D series
Demonstration board for ADC1412D, ADC1212D, ADC1112D
series
Rev. 7 — 6 August 2010
Document information
Info
Content
Keywords
PCB2004-1, Demonstration board, ADC, Converter, ADC1412D,
ADC1212D and ADC1112D series.
Abstract
This document describes how to use the demonstration board for the
analog-to-digital converter ADC1412D, ADC1212D and ADC1112D
series.
Overview
Quick start

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ADC1412D Series and is the answer not in the manual?

Questions and answers

Related Manuals for NXP Semiconductors ADC1412D Series

Summary of Contents for NXP Semiconductors ADC1412D Series

  • Page 1 Quick start ADC1412D, ADC1212D, ADC1112D series Demonstration board for ADC1412D, ADC1212D, ADC1112D series Rev. 7 — 6 August 2010 Quick start Document information Info Content Keywords PCB2004-1, Demonstration board, ADC, Converter, ADC1412D, ADC1212D and ADC1112D series. Abstract This document describes how to use the demonstration board for the analog-to-digital converter ADC1412D, ADC1212D and ADC1112D series.
  • Page 2 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Revision history Date Description 20081001 Initial version. 20090518 Update to PCB2004-1.2. 20090610 Add SPI software description. 20100518 Update to latest release of SPI software. Add HSDC extension module acquisition system description.

  • Page 3: Adc1112D Demo Board

    1. Overview of the ADC1412D, ADC1212D, ADC1112D demo board 1.1 ADC1412D series Figure 1 presents the connections to measure the ADC1412D series: . 3V .GND OWER SUPPLY OWER SUPPLY SYNTHESIZED . I = 370 mA .GND .1.8V . I = 40 mA...

  • Page 4: Adc1212D Series

    1.2 ADC1212D series Figure 2 presents the connections to measure the ADC1212D series: .GND . 3V OWER SUPPLY OWER SUPPLY SYNTHESIZED .1.8V . I = 370 mA .GND . I = 40 mA SIGNAL GENERATOR NPUT SIGNAL ILTER . 2V sinewave .

  • Page 5: Adc1112D Series

    1.3 ADC1112D series Figure 3 presents the connections to measure the ADC1112D series: .GND . 3V OWER SUPPLY OWER SUPPLY SYNTHESIZED .1.8V . I = 370 mA .GND . I = 40 mA SIGNAL GENERATOR NPUT SIGNAL ILTER . 2V sinewave .

  • Page 6: Power Supply

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 1.4 Power supply The board is powered with a 3 V and 1.8/3 V power supplies. A power supply regulator is used to supply all the circuitry on the board.

  • Page 7: Output Signals (Da0 To Da13, Db0 To Db13, Otra, Dav)

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 1.6 Output signals (DA0 to DA13, DB0 to DB13, OTRA, DAV) The digital output signal is available in binary, 2’s complement or gray format. A Data Valid Output clock (DAV) is provided by the device for the data acquisition.

  • Page 8: Spi Program

    1.8.2 ADC1412D driver application The panel driver for the ADC1412D series has 6 pages dedicated to various purposes. The button “QUIT” will close the driver application (refer to as ADC1x1x.vi in window title) and turn off the main application. To restart the application, click on the arrow.

  • Page 9: Page Write Single

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Restart application Fig 6. SPI main window: click on arrow to restart the application 1.8.2.1 Page Write single This page allows writing on register at a time: Fig 7. SPI main window: write page This can be done by either: •...

  • Page 10: Page Flexible

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 8. SPI main window: global page Perform any settings and then click on the “send” button to update the ADC1412D registers. 1.8.2.3 Page Flexible This page allows getting access to the bit definition of remaining registers as defined in the datasheet: QS_ADC1412D_7.doc...

  • Page 11: Page Read

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 9. SPI main window: flexible page Perform any settings and then click on the “send” button to update the ADC1412D registers. 1.8.2.4 Page Read This page allows reading the ADC1412D registers: QS_ADC1412D_7.doc...
  • Page 12 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 10. SPI main window: read page This can be done either: • enter the address in field : the value will be automatically displayed in field (both fields shows values in hexadecimal by default);...

  • Page 13: Page Compare Adc A&B

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Column 1 Column 2 Column 3 Offset Test pattern 1 Test pattern 2 Test pattern 3 Fast OTR CMOS output LVDS DDR O/P 1 LVDS DDR O/P 2 Note that all data are saved in hexadecimal format.
  • Page 14 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 12. SPI main window: compare ADC A&B page To do the comparison, follow the procedure below: • Select the first register and last register to be compared (buttons •...
  • Page 15 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 13. SPI main window: compare ADC A&B page, comparison result example Click on the “save to file” button to save the result of the comparison: this will display a window to select the file to store data to: Fig 14.

  • Page 16: Page Load File

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Table 6. Typical saving for comparison on text file Content of file is shown as table format Column 1 Column 2 Column 3 Register Name ADC A ADC B Channel index...
  • Page 17 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 15. SPI main window: load file page It is not necessary to have a file that has the whole set of registers listed. The only restriction is regarding the formatting of the file as given in section 1.5.2.4.
  • Page 18 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 16. SPI main window: load file page, successful download performed QS_ADC1412D_7.doc © NXP B.V. 2010. All rights reserved. Quick start Rev. 7 — 6 August 2010 18 of 41...

  • Page 19: Hsdc Extension Module: Acquisition Board

    2. HSDC extension module: acquisition board figure 17 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board: +5V P OWER SUPPLY . I = 3.2A UMPER FOR SUPPLY . define either I/O is 1.8V or 3.3V SIGNAL GENERATOR EFERENCE SIGNAL .

  • Page 20: Hsdc Extension Module: Hardware Initialization

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start The HSDC extension module is intended for acquisition/generation and clock generation purpose. When connected to an ADC demo-board it is intended as an acquisition system for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR (SAMTEC QTH_060_02 P2 connector).

  • Page 21: Hsdc Extension Module: Cmos Connector Description

    Click “Next” to continue: Fig 20. “USBConfigSetup” window: step 3 Click “Next” to finish the installation process. The system is now ready to use the ADC1412D series board for evaluation purpose. 2.3 HSDC extension module: CMOS connector description figure 21...
  • Page 22 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 21. HSDC extension module: HE14 CMOS hardware schematic overview The HSDC extension module can acquire data in CMOS level using: • either the on-board clock generated by the internal PLL, refer to as pDFS_CLK[0]/nDFS_CLK[0] that will be used by the FPGA.

  • Page 23: Hsdc Extension Module: Lvds Ddr Connector Description

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start • or the clock provided by the ADC refer to as P1_CLK_IN. This is the preferred situation since the user will not deal with any set-up/hold timing for the acquisition.
  • Page 24 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start The HSDC extension module can acquire data in LVDS DDR arranging in interleaved mode with 2 possible clock edge configurations: • Rising edge as shown below: Fig 23. HSDC extension module: LVDS DDR interleaved data bit rising edge acquired •...

  • Page 25: Combo Adc1412D And Hsdc Extension Module

    3. Combo ADC1412D and HSDC extension module 3.1 ADC1412D CMOS outputs figure 25 below shows an overview of the whole system ADC1412D+HSDC extension module with CMOS outputs configuration for which connection is straightforward, together with a supply extension module (release A) for the ADC1412D demo-board: +5 V POWER SUPPLY RESENTED CONFIGURATION...

  • Page 26: Adc1412D Lvds Outputs

    3.2 ADC1412D LVDS outputs figure 26 below shows an overview of the whole system ADC1412D+HSDC extension module with LVDS outputs configuration for which connection is done with a bridge SAMTEC, together with a supply extension module (release B) for the ADC1412D demo-board: +5 V POWER SUPPLY .

  • Page 27: Hsdc Extension Module: Fpga Flash

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 3.3 HSDC extension module: FPGA flash To get access to the software control of the generation system, run the “USB Configurator.exe”. It is located by default in the directory "C:\Program Files\Electronique Concept\USB Configurator\".

  • Page 28: Hsdc Extension Module: Pattern Acquisition

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 28. “USB Configurator” window: DATA clock configuration The FPGA configuration indicates which configuration file has been programmed in FPGA, in the example shown it is the rising edge of the clock on port P2.

  • Page 29: Use Case Adc1412D Series

    Quick start 3.5.1.1 Use case ADC1412D series The hardware connection between the ADC1412D series and the HSDC extension module has to be described to get correct results. This is done by using the fields in “Channel 0 Input Configuration” and in “Channel 1 Input Configuration”.

  • Page 30: Use Case Adc1112D Series

    31). Fig 31. “USB Configurator” window: pattern acquisition for ADC1112D series 3.5.2 Acquisition in LVDS mode The ADC1412D series (as well as ADC1212D and ADC1112D series) delivers data in LVDS DDR corresponding in 2 possible configuration (bit-wise or byte-wise). QS_ADC1412D_7.doc ©...
  • Page 31 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start The hardware connection between the 2 boards is done such that: • CH0[7] and CH1[0] are not used and fixed to zero; • CH0[0..6] is ADCB from ADC1412D, the polarity of each individual bit is inverted;...

  • Page 32: Pattern Acquisition

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 34. “USB Configurator” window: pattern acquisition for all series Note: to get correct data it is relevant to set the correct clock delay delivered by the ADC1412D, ADC1212D and ADC1112D series (see...

  • Page 33: Acquisition Software: Input Files

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 35. “NXP_ADC_Acquisition” window: start-up screen 3.6.1 Acquisition software: input files The first step consists in delivering the files to be processed. Browse in field “Select ADC1 file:” and/or in field “Select ADC2 file:” to indicate the files to be used.

  • Page 34: Acquisition Software: Fft Results Display

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 36. “NXP_ADC_Acquisition” window: frequency entry 3.6.3 Acquisition software: FFT results display Press the “COMPUTE” button to display the results from the FFT processing. The results fields will be updated depending on the number of input files. If 2 files have been processed, it is possible to display both results on the same picture for all graphs using the “Display …”...

  • Page 35: Overview Of The Adc1412D, Adc1212D, 3.6.3.2 Reorganized Signal

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 37. “NXP_ADC_Acquisition” window: FFT result Press the “Autoscale” button to display the whole content. The tables give the relevant dynamic parameters: • Table : first 6 harmonics frequencies and amplitude level;...

  • Page 36: Unreconstruted Signal

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 38. “NXP_ADC_Acquisition” window: reorganized signal Press the “Autoscale” button to display the whole content. 3.6.3.3 Unreconstruted signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule: QS_ADC1412D_7.doc...

  • Page 37: Histogram

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Zoom tool Fig 39. “NXP_ADC_Acquisition” window: unreconstruted signal Press the “Autoscale” button to display the whole content. Use the zoom tool to observe in more details all the captured data.
  • Page 38 NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 40. “NXP_ADC_Acquisition” window: code histogram Press the “Autoscale” button to display the whole content. The table shows the range of output codes. QS_ADC1412D_7.doc © NXP B.V. 2010. All rights reserved.

  • Page 39: Appendix A.1: Coherency Calculation

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 4. Appendix A.1: coherency calculation The coherency relies on the fact that clock and analog input signal are synchronized and the first and last samples being captured are adjoining samples: it ensures a continuous digitized time process for the FFT processing.

  • Page 40: Notes

    NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 5. Notes For any question, feel free to contact us at the following e-mail dataconverter- support@nxp.com. QS_ADC1412D_7.doc © NXP B.V. 2010. All rights reserved. Quick start Rev. 7 — 6 August 2010...

  • Page 41: Table Of Contents

    HSDC extension module: FPGA flash....27 HSDC extension module: DATA clock configuration.............27 HSDC extension module: pattern acquisition...28 3.5.1 Acquisition in CMOS mode ......28 3.5.1.1 Use case ADC1412D series......29 3.5.1.2 Use case ADC1212D series......29 3.5.1.3 Use case ADC1112D series......30 3.5.2 Acquisition in LVDS mode........30 3.5.3...

This manual is also suitable for:

Adc1212d seriesAdc1112d series

Table of Contents