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PSoC™ 4 MCU low-power modes and power reduction techniques
Other low-power mode considerations
savings from reducing the TCPWM clock is mostly linear based on clock frequency.
comparison between the clock settings for the TCPWM block.
High-power
scheme
Low-power
scheme
Figure 8
TCPWM clock settings comparison
The TCPWM block has a clock prescaler feature. For minimum power consumption, maximize the peripheral
clock divider Clk_Peri before using the TCPWM clock prescaler.
6.5
SAR ADC
If the full-rated accuracy of ADC results is not required, use a lower resolution and do not use averaging, which
reduces the number of ADC clocks required for the same sample rate.
If the maximum sample rate is not required, consider using the single-shot mode instead of continuous mode.
This avoids the SAR ADC operating all the time. In single shot mode, the ADC samples only when triggered by
software or hardware.
6.6
Deep sleep and hibernate regulators
PSoC™ 4 MCU has two low-power regulators that are used to maintain logic states in deep sleep and hibernate:
The deep sleep regulator supplies the circuits that remain powered in deep sleep mode, such as the ILO and
•
SCB. The deep sleep regulator is available in all power modes except the hibernate mode. In active and
sleep power modes, the main output of this regulator is connected to the output of the active digital
regulator (V
). This regulator also has a separate replica output that provides a stable voltage for the ILO.
CCD
This output is not connected to V
The hibernate regulator supplies the circuits that remain powered in hibernate mode, such as the sleep
•
controller, low-power comparator, and SRAM. The hibernate regulator is available in all power modes. In
active and sleep modes, the output of this regulator is connected to the output of the digital regulator. In
deep sleep mode, the output of this regulator is connected to the output of the deep sleep regulator.
Neither of these regulators powers the V
is not brought out on a pin of the device.
Application Note
HFCLK
CLK/2
24 MHz
HFCLK
CLK/2
24 MHz
in active and sleep modes.
CCD
supply. Each regulator powers an internal power supply domain and
CCD
19 of 38
Clk_TCPWM
Clk_Peri
CLK/16
16 MHz
Clk_TCPWM
Clk_Peri
CLK/128
16 MHz
Figure 8
shows a
1 MHz
1 Hz
Period =
1000000
125 KHz
1 Hz
Period =
125000
001-86233 Rev. *I
2021-11-04
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