(Fun18) - FATEK FBS Series Manual

FUN 18 D P
AND
WX WY
Range
WX0 WY0
Ope-
∣ ∣
rand
WX240 WY240 WM1896
Sa
○ ○
Sb
○ ○
D
○
Performs logical AND operation for the data of Sa and Sb when the operation control input "EN" =1 or "EN↑"
●
P
( instruction) from 0 to 1. This operation compares the corresponding bits of Sa and Sb (B0~B15 or
B0~B31). The bit in the D is set to 1 if both of the corresponding bits data of Sa and Sb is 1. The bit in the D is
set to 0 if one of the corresponding bits is 0.
Example
Operation of 16-bit logical AND
Ladder diagram
X0
EN
WM WS TMR CTR
WM0 WS0 T0 C0
∣ ∣ ∣ ∣
WS984 T255 C255
○ ○ ○ ○
○ ○ ○ ○
○ ○ ○ ○
18P.AND
0
R
Sa : D=0
Sb :
R 1
D : R 2
B15
↓
Sa R0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1
Sb R1 1 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0
B15
↓
D R2 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0
LOGICAL AND
Sa: The register to be ANDed
Sb: The register to be ANDed
D : The register to store the result of AND
The Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing application
HR IR OR HR
R0 R3804 R3904 R3920
∣ ∣ ∣ ∣
R3839 R3903 R3919 R4047
○ ○ ○ ○
○ ○ ○ ○
○ ○ ○
Key operations
ORG

X0＝
6 - 3 5
Basic Function Instruction
Operand
HSCR RTCR SR ROR
R4096 R4128 R4136 R5000
∣ ∣ ∣ ∣
R4127 R4135 R4167 R8071
○ ○ ○ ○
○ ○ ○ ○
○ * ○ *
○ ○
Mnemonic code
ORG
FUN
Sa :
Sb :
D :
B0
↓
B0
↓
FUN 18 D P
AND
DR K
D0
16/32 bit
∣
+/-number
D4095
○ ○
○ ○
○
X 0
18P
R 0
R 1
R 2