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D. Other circuit
[a] EEPROM (IC3) circuit
This circuit serves as a memory to save the sensitivity data of the reflection type sensors, the adjustment values such as the original set position on
the original table, and the counter values such as the number of originals passed. Data communication with the CPU (IC11) is performed with the
3-wire serial interface.
The saved data are maintained even when the power is turned off.
IC3 1 pin is the chip select pin, which is driven to HIGH when data communication is performed.
2 pin is the serial lock pin, and the serial data are transmitted in synchronization with the clock inputted to this pin.
3 pin is the input pin of serial data from the CPU. 4 pin is the output pin of serial data from IC3.
D1, R50, and C1 form a circuit which keeps the power of IC3 at a constant level even when a sudden power drop occurs during data writing.
[b] Reset circuit
This circuit generates reset signals for the CPU and the external G/A, and is composed of IC6 and its peripheral circuits.
IC6 is provided with the reset function activated when the power is turned on and when the power falls below +5V.
The reset state is maintained until a certain time passes from when the power voltage reaches about 4.3V after supplying the power. The reset
maintaining time depends on the capacity of C9.
This circuit is also provided with the watch-dog timer function.
The watch-dog timer is built in the G/A (IC7) and is operated when RES2 turns HIGH. It monitors hung-up or other abnormalities of the CPU. RES2
is reset for the watch-dog timer in the G/A, and is separated from the CPU and RES1 of the G/A by D2. Therefore, the CPU reset and the G/A RES1
do not turn HIGH prior to RES2.
For monitoring, data (initial values) are written from the CPU to the G/A once for every 5ms. (Resetting to the initial values every 5ms.) The data are
counted down inside the G/A. Since the values are reset to the initial values every 5ms, the count normally does not fall to zero. If, however, a
hung-up of the CPU occurs, the data are not reset to the initial values, and the counter becomes zero. At that time, resetting is performed from the
G/A to the CPU and the G/A (RES1), and retry is performed until the CPU is resumed.
To main body via
interface cable
+5V
D1
E2ROM+5V
R49
R50
10
100K
IC3
C1
4
R4
DO
1
R3
CS
100µ F
6
2
R2
SK
ORG
7
3
R1
TEST
DI
ST93C46CM1
+5V
R61
1.0K
DF3-6P-2DSA
R52
CN9-6
RESET
4.7K
C43
0.1µ F
C4
1000PF
+5V
D3
R24
22K
10K
22K
22K
22K
R8
R42
R41
10K
10K
10K
EEPROM circuit
+5V
R58
4.7K
D6
Q5
2SC2712
DSA010
R30
10K
+5V
+5V
R5
7
IC6
IC5.3
22K
D2
VCC
5
6
6
C
OUT
GND
SB02-030
HD74LS06FP
C9
4
M51953BFP
0.33µ F
Reset circuit
– 35 –
CPU
(IC11)
60
P74/ANI4
51
P14
52
P15
50
P13
CPU
TP18
(IC11)
7
*RESET
C44
0.1µ F
G/A
(IC7)
37
RES1
C42
+5V
0.1µ F
TP23
R9
10K
5
38
WDT
39
RES2
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