Aaeon PICO-EHL4 User Manual
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Aaeon PICO-EHL4 User Manual

Pico-itx single board computer
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PICO-EHL4
PICO-ITX Single Board Computer
st
User 's Manual 1
Ed
Last Updated: October 21, 2021

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Summary of Contents for Aaeon PICO-EHL4

  • Page 1 PICO-EHL4 PICO-ITX Single Board Computer User ’s Manual 1 Last Updated: October 21, 2021...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel®, Celeron® and Pentium® are registered trademarks of Intel Corporation ⚫ Intel Atom™ is a trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: I t em Quantity PICO-EHL4 MB ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page on AAEON.com for the latest version of this document. Preface...
  • Page 6 Saf e ty Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 Chi na RoHS Requirements ( CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (C d) (C r(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○...
  • Page 10 Chi na RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements He xavalent Polybrominated Polybrominated C omponent Le ad Me rcury C admium C hromium Biphenyls...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..............1 Specifications ....................
  • Page 12 2.4.18 Power Input +12V (CN20).............. 28 2.4.19 Front Panel (CN21) ................. 28 2.4.20 DC Jack Power I nput (Reserved) (CN22) ........28 2.4.21 RJ45 Connector (Reserved)............29 Thermal Assembly Options ................30 2.5.1 Active Cooling Fan FAN01.............. 30 2.5.2 Fan-less Heatspreader HSP01............31 2.5.3 Heatsink HSK01 (with Heatspreader)..........
  • Page 13 Appendix C - Watchdog Timer Programming ..........86 Introduction to Watchdog Timer ..............87 Programing the Watchdog Timer with AAEON SDK ........88 Programing Watchdog Timer with AAEON Windows EAPI ....... 89 C.3.1...
  • Page 14 C.3.1.7 EapiWDogSetStatus()............94 Preface...

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    1 .1 Spe cifications System F o rm Factor PICO-ITX CP U Intel® Atom™ x6000E series, Intel® Pentium and Celeron® N and J series processors Intel® Atom™ x6425RE (4C, 1.9GHz, TDP 12W) Intel® Atom™ x6414RE (4C, 1.5GHz, TDP 9W) Intel® Atom™ x6212RE (2C, 1.2GHz, TDP 6W) Intel®...
  • Page 17 System B I OS AMI UEFI W ake On LAN W atchdog Timer 255 Levels P o wer Requirement +12V AT/ATX (default) P o wer Supply Type Lockable & Phoenix Terminal co-lay P o wer Consumption (Typical) Intel® Pentium® J6426, LPDDR4x onboard 8GB: 2.36A at +12V (balance), 2.81A at +12V (max) Intel®...
  • Page 18 Di splay Chip set Intel® Atom™ x6000E series, Intel® Pentium and Celeron® N and J series processors R esolution HDMI2.0b x 2, 4K 60Hz Single channel 12V/3.3V, 18/24-bit LVDS/eDP up to 4K LCD I nterface 18/24-bit Single LVDS St orage/SSD eMMC x 1 (32/64/128 GB) SATA III (6.0 Gbps) x 1 SATA Power (5V) x 1...

  • Page 19: Function Block Diagram

    1 .2 Function Block Diagram Chapter 1 – Product Specifi c ations...

  • Page 20: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 21: Dimensions

    Di mensions Chapter 2 – Hardware Information...

  • Page 22: Jumpers And Connectors

    2.2 Jum pers and Connectors Chapter 2 – Hardware Information...
  • Page 23 Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers

    2.3 Li st of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Lab el F unction JP 1 Clear CMOS Jumper, Auto Power Button Selection 2.3.1 Cl e ar CMOS Jumper, Auto Power Button Selection (JP1) Clear CMOS Jumper Normal (Default) Clear CMOS...

  • Page 25: List Of Connectors

    2.4 Li st of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Lab el F unction CN 1 RTC Battery Connector CN 2 LVDS Back Light Inverter CN 3 LVDS/eDP [Reserved] CN 4 Dual HDMI Connector...

  • Page 26: Rtc Battery Connector (Cn1)

    2.4.1 RTC Battery Connector ( CN1) P in P in Name Sig nal Type Sig nal Level +3.3V +3.3V 2.4.2 LVDS Back Light Inverter (CN2) P in P in Name Sig nal Type Sig nal Level BLK_PWR +12V (Default)/ +5V BLK_PWR +12V (Default)/ +5V BKL_CONTROL...
  • Page 27 P in P in Name Sig nal Type Sig nal Level LVD1_CA_2_DN/ DIFF EDP_LANE2_DN LVD1_CA_2_DP/ DIFF EDP_LANE2_DP LVD1_CA_1_DN/ DIFF EDP_LANE1_DN LVD1_CA_1_DP/ DIFF EDP_LANE1_DP LVD1_CA_0_DN/ DIFF EDP_LANE0_DN LVD1_CA_0_DP/ DIFF EDP_LANE0_DP LVD1_CA_3_DN/ DIFF EDP_LANE3_DN LVD1_CA_3_DP/ DIFF EDP_LANE3_DP LVD1_CA_CLKN/ DIFF EDP_AUX_DN LVD1_CA_CLKP/ DIFF EDP_ AUX _DP LVD1_BKLCTL/ DDI0_BKLTCTL_R...

  • Page 28: Dual Hdmi Connector (Cn4)

    P in P in Name Sig nal Type Sig nal Level +VCC_EDP_BKLT +12V (Default) / +5V +VCC_EDP_BKLT +12V (Default) / +5V +VCC_EDP_BKLT +12V (Default) / +5V +VCC_EDP_BKLT +12V (Default) / +5V N o te 1: Backlight Power can be 12V or 5V, set by BOM: SKU R466 for 12V and SKU R2679 for 5V (Default is 12V).
  • Page 29 P in P in Name Sig nal Type Sig nal Level DDC_CLK DDC_DATA HDMI_HPD HDMI_TX2+ DIFF HDMI_TX2- DIFF HDMI_TX1+ DIFF HDMI_TX1- DIFF HDMI_TX0+ DIFF HDMI_TX0- DIFF HDMI_CLK+ DIFF HDMI_CLK- DIFF DDC_CLK DDC_DATA HDMI_HPD Chapter 2 – Hardware Information...

  • Page 30: Dual Lan Connector (Cn5)

    2.4.5 Dual L AN Connector (CN5) P in P in Name Sig nal Type Sig nal Level 1P 1 LAN1_MDI0+ DIFF 1P 2 LAN1_MDI0- DIFF 1P 3 LAN1_MDI1+ DIFF 1P 4 LAN1_MDI1- DIFF 1P 5 1P 6 1P 7 LAN1_MDI2+ DIFF 1P 8 LAN1_MDI2-...

  • Page 31: Sata Port (Cn6)

    P in P in Name Sig nal Type Sig nal Level LAN2_LED_LNK#_ACT Signal +V3P3A 3.3V LAN2_LED_100# Signal LAN2_LED_1000# Signal 2.4.6 SATA Port (CN6) P in P in Name Sig nal Type Sig nal Level SATA_1_TXP DIFF SATA_1_TXN DIFF SATA_1_RXN DIFF SATA_1_RXP DIFF 2.4.7...

  • Page 32: Dio 4-Bit Header (Cn8)

    2.4.8 DIO 4-bit Header ( CN8) P in P in Name Sig nal Type Sig nal Level +V5S DIO_0 Signal DIO_1 Signal DIO_2 Signal DIO_3 Signal N o te: CN8 DIO power max current: 0.5A. 2.4.9 USB2.0/ USB3.2 Dual Port (Port 1 / Port 2) (CN9) P in P in Name Sig nal Type...

  • Page 33: Usb2.0 Dual Port Header (Cn10)

    P in P in Name Sig nal Type Sig nal Level USB3_1_RXN DIFF USB3_1_RXP DIFF USB3_1_TXN DIFF USB3_1_TXP DIFF N o te: CN9 USB Power max current: 2.0A , 1.0A for each port. 2.4.10 USB2.0 Dual Port Header (CN10) P in P in Name Sig nal Type Sig nal Level...

  • Page 34: Msata/ Mini Card Slot (Cn11)

    2.4.11 mSATA/ Mini Card Slot ( CN11) P in P in Name Sig nal Type Sig nal Level PCIE_WAKE# +3.3V +3.3V +1.5V +1.5V PCIE_CLK_REQ# PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX-/SATA_RX+ DIFF +3.3V +3.3V Chapter 2 – Hardware Information...
  • Page 35 P in P in Name Sig nal Type Sig nal Level PCIE_RX+/SATA_RX- DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX-/SATA_TX- DIFF SMB_DATA +3.3V PCIE_TX+/SATA_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3V +3.3V +3.3V +3.3V +1.5V +1.5V Chapter 2 – Hardware Information...

  • Page 36: E-Key Slot (Cn12)

    P in P in Name Sig nal Type Sig nal Level +3.3V +3.3V 2.4.12 M.2 E-Key Slot (CN12) P in P in Name Sig nal Type Sig nal Level +V3P3A 3.3V USB2_4_DP DIFF +V3P3A 3.3V USB2_4_DN DIFF Chapter 2 – Hardware Information...
  • Page 37 P in P in Name Sig nal Type Sig nal Level PCIE_2_TXP DIFF PCIE_2_TXN DIFF PCIE_2_RXP DIFF PCIE_2_RXN PCIE_0_CLK_DP DIFF PCIE_0_CLK_DN DIFF BUF_PLT_RST# Signal PCIE_CLKREQ#0 Signal SOC_BT_EN Signal Chapter 2 – Hardware Information...
  • Page 38 P in P in Name Sig nal Type Sig nal Level PCIE_WAKE# Signal SOC_WIFI_EN Signal +V3P3A 3.3V +V3P3A 3.3V Chapter 2 – Hardware Information...

  • Page 39: Can Bus Dual Port Header (Cn13)

    2.4.13 CAN Bus Dual Port Header (CN13) P in P in Name Sig nal Type Sig nal Level +V5A +V3P3A +3.3V CAN0_TX CAN0_RX CAN1_TX CAN1_RX 2.4.14 COM Dual Port Header (CN15) P in R S232 Signal R S422 Signal R S485 Signal DCD_1 TX_1- DATA_1-...

  • Page 40: Spi Port (Cn17)

    P in R S232 Signal R S422 Signal R S485 Signal CTS_1 CTS_2 RI_1/12V/5V RI_2/12V/5V UART_TX UART_RX N o te 1: COM RS-232/ 422/ 485 mode can be set by BIOS. Default is RS-232. N o te 2: RI1/+5V/+12V can be set by BOM (R423 RI/ R369 +12V/ R370 +5V). Default is RING.

  • Page 41: Espi/ Smbus/ I2C

    2.4.16 e SPI/ SMBus/ I2C P in P in Name Sig nal Type Sig nal Level ESPI_IO0 IN/OUT +1.8V ESPI_IO1 IN/OUT +1.8V ESPI_IO2 IN/OUT +1.8V ESPI_IO3 IN/OUT +1.8V +V3.3S +3.3V ESPI_CS Signal ESPI_RESET# +1.8V ESPI_CLK 1.8V SMB_DATA/ I2C_SDA IN/OUT +3.3V SMB_CLK/ I2C_CLK +3.3V SMB_ALERT/...

  • Page 42: Power Input +12V (Cn20)

    2.4.18 Powe r Input +12V (CN20) P in P in Name Sig nal Type Sig nal Level +V_IN +12V 2.4.19 Front Panel ( CN21) P in P in Name Sig nal Type Sig nal Level EXT_PWRBTN# Signal FP_IDELED# Signal +V3P3S +3.3V FP_BUZZER Signal...

  • Page 43: Rj45 Connector (Reserved)

    2.4.21 RJ45 Connector (Reser ved) P in P in Name Sig nal Type Sig nal Level 1P 1 LAN1_MDI0+ DIFF 1P 2 LAN1_MDI0- DIFF 1P 3 LAN1_MDI1+ DIFF 1P 4 LAN1_MDI1- DIFF 1P 5 1P 6 1P 7 LAN1_MDI2+ DIFF 1P 8 LAN1_MDI2- DIFF...

  • Page 44: Thermal Assembly Options

    2.5 T he rmal Assembly Options 2.5 .1 Active Cooling Fan FAN01 Active Cooling Fan, Part Number: PICO-EHL4-FAN01 Chapter 2 – Hardware Information...

  • Page 45: Fan-Less Heatspreader Hsp01

    2.5 .2 Fan-less Heatspreader HSP01 Heat spreader/ fan-less assembly, Part Number: PICO-EHL4-HSP01 Chapter 2 – Hardware Information...

  • Page 46: Heatsink Hsk01 (With Heatspreader)

    2.5 .3 He atsink HSK01 ( with Heatspreader) Heatsink with Heatspreader, Part Number: PICO-EHL4-HSK01 Chapter 2 – Hardware Information...

  • Page 47: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 48: System Test And Initialization

    System Test and Initialization The PICO-EHL4 uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or display an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 49: Ami Bios Setup

    3.2 AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations. These configurations are stored in the battery-backed CMOS RAM and BIOS NVRAM so the information is retained when power is turned off. To enter BIOS Setup, turn on the system and immediately press <Del>...

  • Page 50: Setup Submenu: Main

    3.3 Se tup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 51: Setup Submenu: Advanced

    3.4 Se tup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 52: Cpu Configuration

    3.4.1 CPU Configuration Op tions Summary A ctive Processor Cores All Optimal Default, Failsafe Default Number of cores to enable in each processor package. I nt el (VMX) Disabled Vir tualization Enabled Optimal Default, Failsafe Default Technology When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 53: Pch-Fw Configuration

    3.4.2 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 54: Firmware Update Configuration

    3.4.2.1 Fi rmware Update Configuration Op tions Summary Me F W Image Re-Flash Enabled Disabled Optimal Default, Failsafe Default Enable/Disable Me FW Image Re-Flash function. F W Update Disabled Enabled Optimal Default, Failsafe Default Enable/Disable ME FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 55: Trusted Computing

    3.4.3 Trusted Computing Op tions Summary Security Deice Support Enable Optimal Default, Failsafe Default Disable Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Optimal Default, Failsafe Default Enabled...
  • Page 56 Op tions Summary Pending operation None Optimal Default, Failsafe Default TPM Clear Schedule an Operation for the Security Device. NOTE: Y our Computer will reboot during restart in order to change State of Security Device. P latform Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Platform Hierarchy St orage Hierarchy...

  • Page 57: Sata Configuration

    3.4.4 SATA Configuration Op tions Summary SATA Controller(s) Enabled Optimal Default, Failsafe Default Disabled Enable/Disable SATA Device. Po rt* Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SATA Port. Chapter 3 – AMI BIOS Setup...

  • Page 58: Sdio Configuration

    3.4.5 SDIO Configuration Op tions Summary eMMC 5.1 Controller Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SCS eMMC 5.1 Controller SDI O Access Mode Auto Optimal Default, Failsafe Default ADMA SDMA Auto Option: Access SD device in DMA mode if controller supports it , otherwise in PIO mode.

  • Page 59: Hardware Monitor

    3.4.6 Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 60: Smart Fan Mode Configuration

    3.4.6.1 Sm ar t Fan Mode Configuration Op tions Summary Fan1 Output Mode Output PWM mode (open drain) Output PWM mode Optimal Default, Failsafe Default (push pull) Output PWM mode (push pull) to control 4-wire fans.\nLinear fan application circuit to control 3-wire fan speed by fan’s power terminal.\nOutput PWM mode (open drain) to control Intel 4-wire fans.

  • Page 61: Sio Configuration

    3.4.7 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 62: Serial Port Config Uration

    3.4.7.1 Se ri al Port Configuration Op tions Summary U s e This Device Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Serial Port (COM) Po ssible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8; IRQ=3; IO=3F8; IRQ=4; Select an optimal setting for IO device Mo de RS232 Optimal Default, Failsafe Default...

  • Page 63: Power Management

    3.4.8 Powe r Management Op tions Summary Po wer Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. R estore AC Power Last State Optimal Default, Failsafe Default Lo s s Always On Always Off Select power state when power is re-applied after a power failure. R TC wake system Disabled Optimal Default, Failsafe Default...

  • Page 64: Digital Io Port Config Uration

    3.4.9 Di gital IO Port Configuration Op tions Summary DI O Port0~3 Output Optimal Default, Failsafe Default Input Set DIO as Input or Output Out put Level High Optimal Default, Failsafe Default Set output level when DIO pin is output Chapter 3 –...

  • Page 65: Setup Submenu: Chipset

    3.5 Se tup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 66: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Chapter 3 – AMI BIOS Setup...

  • Page 67: Memory Config Uration

    3.5.1.1 Me mor y Configuration Chapter 3 – AMI BIOS Setup...

  • Page 68: Graphics Configuration

    3.5.1.2 G raphics Configuration Op tions Summary I nt ernal Graphics Auto Optimal Default, Failsafe Default Disabled Enabled Keep IGFX enabled based on the setup options. Chapter 3 – AMI BIOS Setup...
  • Page 69 3.5.1.2.1 LVDS Panel Configuration Op tions Summary LVDS Disabled Enabled Optimal Default, Failsafe Default Enable/Disable this panel. LVDS Panel Type 640X480@60HZ 800X480@60HZ 800X600@60HZ 1024X600@60HZ 1024X768@60HZ Optimal Default, Failsafe Default 1280X768@60HZ 1280X800@60HZ 1280X1024@60HZ 1366X768@60HZ 1440X900@60HZ Select panel type Table Continues on Next Page… Chapter 3 –...
  • Page 70 Op tions Summary Co lor Depth 18-bit Optimal Default, Failsafe Default 24-bit Select Color Depth B acklight Mode Windows Slider Optimal Default, Failsafe Default BIOS & Application Select backlight control signal type B acklight Type Normal Optimal Default, Failsafe Default Inverted Select backlight control signal type B acklight Level...

  • Page 71: Pch-Io Configuration

    3.5.2 PCH-IO Configuration Op tions Summary HD A udio Enabled Optimal Default, Failsafe Default Disabled Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled. F ull-MiniCard Slot SATA Optimal Default, Failsafe Default F unction(CN11) PCIe Select function enabled for Full-MiniCard(CN11) Slot...

  • Page 72: Setup Submenu: Security

    3.6 Se tup Submenu: Security Change User/Administrator Password Y ou can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 73: Secure Boot

    3.6 .1 Se cure Boot Op tions Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset Secure Boot Mode Custom...

  • Page 74: Key Management

    3.6.1.1 Ke y Management Op tions Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode R estore Factory Keys Force System to User Mode. Install factory default Secure Boot key databases R eset To Setup Mode Delete all Secure Boot key databases from NVRAM Exp ort Secure Boot variables...
  • Page 75 Op tions Summary R emove 'UEFI CA' from DB Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db) R estore DB defaults Restore DB variable to factory defaults Secure Boot Variables Enroll Factory Defaults or load certificates from a file: 1.

  • Page 76: Setup Submenu: Boot

    3.7 Se tup Submenu: Boot Op tions Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Quiet Boot option. N etwork Stack Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. I P v4 PXE Support Disabled Optimal Default, Failsafe Default Enabled...

  • Page 77: Setup Submenu: Save & Exit

    3.8 Se tup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 78: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 79: Drivers Download And Installation

    Dri vers Download and Installation Drivers for the PICO-EHL4 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/pico-itx-turnkit-pico-EHL4 Download the driver(s) you need and follow the steps below to install them . St ep 1 – Install Chipset Driver Open the I nt el Chipset folder.
  • Page 80 St ep 4 – Install ME Driver Open the ME folder. Run the Set upME.exe file Follow the instructions Driver will be installed automatically St ep 5 – Install LAN Driver Open the LA N folder. Run the I ns tall_Win10_10050_08132021.exe file Follow the instructions Driver will be installed automatically St ep 6 –...

  • Page 81: Appendix A - Mating Connectors

    Appendix A Appendix A – Mating Connectors...

  • Page 82: Li St Of Mating Connectors And Cables

    Li st of Mating Connectors and Cables The following table lists mating connectors and available cables. Mat ing Connector Co nnector A vailable F unction Cab le P/N Lab el Cab le Vendor Mo del no CN 1 RTC Battery Molex 51021-0200 Battery...

  • Page 83: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 84: Direct Memory Access (Dma) Map

    Di rect Memor y Access (DMA) Map Appendix B – I/O Informati o n...

  • Page 85: I/O Address Map

    B.2 I/O Address Map Appendix B – I/O Informati o n...

  • Page 86: Irq Mapping Chart

    B.3 IRQ Mapping Chart Appendix B – I/O Informati o n...
  • Page 87 Appendix B – I/O Informati o n...
  • Page 88 Appendix B – I/O Informati o n...
  • Page 89 Appendix B – I/O Informati o n...
  • Page 90 Appendix B – I/O Informati o n...
  • Page 91 Appendix B – I/O Informati o n...
  • Page 92 Appendix B – I/O Informati o n...
  • Page 93 Appendix B – I/O Informati o n...
  • Page 94 Appendix B – I/O Informati o n...
  • Page 95 Appendix B – I/O Informati o n...
  • Page 96 Appendix B – I/O Informati o n...

  • Page 97: Large Memory Map

    B.4 Large Memory Map Appendix B – I/O Informati o n...

  • Page 98: Memory Address Map

    B.5 Me m or y Address Map Appendix B – I/O Informati o n...
  • Page 99 Appendix B – I/O Informati o n...

  • Page 100: Appendix C - Watchdog Timer Programming

    Appendix C Appendix C - Watchdog Timer Programming...

  • Page 101: Introduction To Watchdog Timer

    Introduction to Watchdog Timer This section details how to set up and program the Watchdog Timer for your AAEON system or board. The watchdog timer is used to automatically detect malfunctions and recover the system. During normal operation, the system will regularly send a signal to reset the watchdog timer.

  • Page 102: Programing The Watchdog Timer With Aaeon Sdk

    C.2 Programing the Watchdog Timer with AAEON SDK If you have installed the AAEON Framework, you can program the Watchdog Timer using the AAEON SDK. Simply locate where the SDK is installed, and double click the icon. The following dialog box will appear: Co unt Mode: Set Watchdog Timer to count in minutes or seconds.

  • Page 103: Programing Watchdog Timer With Aaeon Windows Eapi

    C.3 Programing Watchdog Timer with AAEON W indows EAPI AAEON Framework (KMDF Driver) must be installed before calling these functions. EapiLibInitialize() should be the first to call before calling other EAPI functions. EApiLibUnInitialize() should be called to release resources before program exit.

  • Page 104: Watchdog Timer Functio Ns

    EApiWDogStop must be called before Stage C/F to prevent event from being generated. EApiWDogStop must be called before Stage D/G to prevent system from being reset. C.3.1 Watchdog T imer Functions C.3.1.1 E apiWDogGetCap() Command Line: EApiWDogGetCap(…) __OUTOPT uint32_t *pMaxDelay, __OUTOPT uint32_t *pMaxEventTimeout, __OUTOPT uint32_t *pMaxResetTimeout Use this command to get maximum Supported Delay / Supported Event Timeout /...

  • Page 105: Eapiwdogstart()

    C.3.1.2 E apiWDogStart() Command Line: EApiWDogStart( __IN uint32_t Delay, __IN uint32_t Minute, __IN uint32_t EventTimeout, __IN uint32_t ResetTimeout Use this command to start the Watchdog Timer and set the timeout values. To stop the Watchdog Timer, issue the command EApiWDogStop. After issuing EAPiWDogStop, the command EApiWDogStart must be called again with new values to restart.

  • Page 106: Eapiwdogtrigger()

    C.3.1.3 E apiWDogTrigger() Command Line: EapiWDogTrigger() Use this command to trigger the Watchdog Timer. Parameters F unction Parameters None Co ndition R eturn Values Library Uninitialized EAPI_STATUS_NOT_INITIALIZED Watchdog Not Started EAPI_STATUS_ERROR Common Error Common Error Code Others EAPI_STATUS_SUCCESS C.3.1.4 E apiWDogStop() Command Line: EapiWDogStop() Use this command to close the Watchdog Instance.

  • Page 107: Eapiwdogreloadtimer()

    C.3.1.5 E apiWDogReloadTimer() Command Line: EapiWDogReloadTimer() Use this command to reload the Timeout count Parameters F unction Parameters None Co ndition R eturn Values Library Uninitialized EAPI_STATUS_NOT_INITIALIZED Common Error Common Error Code Others EAPI_STATUS_SUCCESS C.3.1.6 E apiWDogGetStatus() Command Line: EapiWDogGetStatus( __OUTOPT uint32_t *pwdtMinute, __OUTOPT uint32_t *pwdtCountTime, __OUTOPT uint32_t *pwdtReloadTime...
  • Page 108 C.3.1.7 E apiWDogSetStatus() Command Line: EApiWDogSetStatus( __IN uint32_t wdtMinute, __IN uint32_t wdtCountTime, __IN uint32_t wdtReloadTime Use this command to set Watchdog Timer mode, time count value and reload timer. Parameters F unction Parameters wdtMinute Set the mode of minute or second wdtCountTime Set WDT time count wdtReloadTime...

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