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Aaeon PICO-APL1 User Manual

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PICO-APL1
PICO-APL1 Single-Board Computer
User's Manual 1
st
Ed
Last Updated: June 21, 2017

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  • Page 1 PICO-APL1 PICO-APL1 Single-Board Computer User’s Manual 1 Last Updated: June 21, 2017...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ®  ITE is a trademark of Integrated Technology Express, Inc.  IBM, PC/AT, PS/2, and VGA are trademarks of International Business Machines ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity PICO-APL1  Product DVD with drivers  Heat Spreader (optional)  COM + Line-out Cable (optional)  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................8 List of Jumpers ......................10 2.3.1 Clear CMOS Jumper (JP1 1, 3, 5) .............. 11 2.3.2 Auto Power Button Enable/Disable Selection (JP1 2, 4, 6) ....
  • Page 12 2.4.14 LVDS Port (CN16) ..................25 2.4.15 COM Port 1/2 & line out connector (CN17) ........27 2.4.16 COM port2 RS-485 ................. 28 2.4.17 COM port2 RS-422 ................. 29 2.4.18 LPC port2 (CN18) ..................29 2.4.19 USB 2.0 Port 1 (CN19) ................30 2.4.20 Specifications for I/O Port ................
  • Page 13 Product CD/DVD ....................57 Appendix A - Watchdog Timer Programming ..............59 Watchdog Timer Registers .................. 60 Watchdog Sample Program ................. 61 Appendix B - I/O Information ....................64 I/O Address Map ....................65 Memory Address Map ..................66 IRQ Mapping Chart ....................67 Appendix C –...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System PICO-APL1 Form Factor  Intel® Pentium Processor N4200 Processor  Intel® Celeron Processor N3350 204-pin DDR3L 1600/1333MHz SODIMM x 1, System Memory  max up to 8 GB Intel® Pentium N4200/Celeron N3350 Chipset  integrated AMI / SPI BIOS ...
  • Page 16 Intel® Pentium N4200/Celeron N3350 Chipset  integrated graphic LVDS (18/24bit 2CH) 1920 x 1200 Resolution  HDMI up to 3840 x 2160 DDI (BIO) LVDS (18/24bit) up to 1920 x1200@ 60Hz [select LCD Interface  by BIOS or jumper] HDMI up to 3840 x 2160 @ 30Hz; Or DDI (by BIO Board optional) SATA 6.0Gb/s x 1, Storage...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions Component Side Component Side MATER >0 ¡ Ó 0 .1 SPEC.: >10 ¡ Ó 0 .2 >50 ¡ Ó 0 .3 FINISH: >200 ¡ Ó 0 .5 >500 ¡ Ó 0 .8 UNIT: M ANGLE TOL. SCALE: ¡ Ó 0 .5¢X Chapter 2 –...
  • Page 19 ¡ Ó 0 .2 >50 ¡ Ó 0 .3 NAME PCB drawing FINISH: APPROVED CHECKED DESIGNED >200 ¡ Ó 0 .5 >500 ¡ Ó 0 .8 PICO-APL1 UNIT: MM MODEL No. Kevin Willie ANGLE TOL. A0.3 REV. SHEET: SCALE: ¡ Ó 0 .5¢X...
  • Page 20 Rear I/O Configuration Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Component Side Component Side MATERI >0 ¡ Ó 0 .1 SPEC.: >10 ¡ Ó 0 .2 >50 ¡ Ó 0 .3 FINISH: >200 ¡ Ó 0 .5 >500 ¡ Ó 0 .8 UNIT: M ANGLE TOL. SCALE: ¡...
  • Page 22 ¡ Ó 0 .2 >50 ¡ Ó 0 .3 FINISH: APPROVED CHECKED DESIGNED NAME PCB drawing >200 ¡ Ó 0 .5 >500 ¡ Ó 0 .8 PICO-APL1 UNIT: MM MODEL No. Kevin Willie ANGLE TOL. A0.3 REV. SHEET: SCALE: ¡ Ó 0 .5¢X...

  • Page 23: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function JP1(1,3,5) Clear CMOS Jumper JP1(2,4,6) Auto Power Button Enable/Disable Selection JP2(1,3,5) LVDS Port Operating Voltage Selection JP2(2,4,6) LVDS Port Backlight Inverter Voltage Selection LVDS Port Backlight Lightness Control Mode Selection...

  • Page 24: Clear Cmos Jumper (Jp1 1, 3, 5)

    2.3.1 Clear CMOS Jumper (JP1 1, 3, 5) Normal (Default) Clear CMOS 2.3.2 Auto Power Button Enable/Disable Selection (JP1 2, 4, 6) Enable (Default) Disable 2.3.3 LVDS Port Operating Voltage Selection (JP2 1,3,5) +3.3V (Default) 2.3.4 LVDS Port Backlight Inverter Voltage Selection Selection (JP2 2,4,6) +12V +5V (Default) Chapter 2 –...

  • Page 25: Lvds Port Backlight Lightness Control Mode (Jp3)

    2.3.5 LVDS Port Backlight Lightness Control Mode (JP3) VR Mode (Default) PWM Mode List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Digital IO Port LVDS Port Inverter / Backlight Connector Front Panel Mini-Card Slot (Half-Mini Card)
  • Page 26 CN17 COM Port 1/2 & line out connector CN18 LPC Port CN19 USB 2.0 Port 1 Chapter 2 – Hardware Information...

  • Page 27: Digital Io Port (Cn1)

    2.4.1 Digital IO Port (CN1) Pin Name Signal Type Pin Name DIO0 DIO1 DIO2 DIO3 2.4.2 LVDS Port Inverter / Backlight Connector (CN2) Pin Name Signal Type Signal level BKL_PWR +5V / +12V Chapter 2 – Hardware Information...

  • Page 28: Front Panel (Cn3)

    Pin Name Signal Type Signal level BKL_CONTROL BKL_ENABLE +3.3V ※ LVDS/BKL_PWR can be set to +5V or +12V by JP2. ※ LVDS/BKL_CONTROL can be set by JP3. ※ The driving current supports up to 2A. 2.4.3 Front Panel (CN3) Pin Name Pin Name PWR_BTN- PWR_BTN+...

  • Page 29: Mini-Card Slot (Half-Mini Card) (Cn4)

    2.4.4 Mini-Card Slot (Half-Mini Card) (CN4) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3V +3.3VSB +1.5V +1.5V PCIE_CLK_REQ# PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF Chapter 2 – Hardware Information...
  • Page 30 W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 31: Bio Connector (Cn7)

    +3.3VSB +3.3V +1.5V +1.5V +3.3VSB +3.3V 2.4.5 BIO connector (CN7) Pin Name Pin Name +12VSB PCIE_TXN0 PCIE_RXN0 PCIE_TXP0 PCIE_RXP0 Chapter 2 – Hardware Information...
  • Page 32 Pin Name Pin Name PS_ON# +5VSB +5VSB +5VSB +5VSB PCIE_REF_CLK0 RESET# PCIE_REF_CLK0# USBN0 USBP0 USBN1 USBP2 Chapter 2 – Hardware Information...

  • Page 33: Sata Port (Cn8)

    Pin Name Pin Name SMB_CLK SMB_DATA WAKE# USB_OC0# USB_OC1# LPC_AD0 LPC_FRAME# LPC_AD1 SERIRQ LPC_AD2 LPC_DRQ LPC_AD3 GPIO0 AGND LPC_CLK AUD_LINEOUT_L PME# AUD_LINEOUT_R 2.4.6 SATA Port (CN8) Pin 1 Pin 7 Chapter 2 – Hardware Information...

  • Page 34: Battery (Cn9)

    Pin Name Signal Type Signal Level SATA_TX1+ DIFF SATA_TX1- DIFF SATA_RX1- DIFF SATA_RX1+ DIFF 2.4.7 Battery (CN9) Pin Name Signal Type Signal Level 3.3V +3.3V 2.4.8 LAN (RJ-45) Port (CN10) ACT/LINK SPEED Chapter 2 – Hardware Information...

  • Page 35: Usb3.0 Ports 0 And 1 (Cn11)

    Pin Name Signal Type Signal Level DIFF MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- 2.4.9 USB3.0 Ports 0 and 1 (CN11) Pin Name Signal Type Signal Level +5VSB DIFF USB0_D- DIFF USB0_D+ USB0_SSRX−...

  • Page 36: Output For Sata Hdd (Cn12)

    DIFF USB1_D- DIFF USB1_D+ USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF 2.4.10 +5V Output for SATA HDD (CN12) Pin Name Signal Type Signal Level Chapter 2 – Hardware Information...

  • Page 37: Hdmi Port (Cn13)

    2.4.11 HDMI Port (CN13) Pin Name Signal Type Signal level TMDS_DAT2+ DIFF TMDS_DAT2- DIFF TMDS_DAT1+ DIFF TMDS_DAT1- DIFF TMDS_DAT0+ DIFF TMDS_DAT0- DIFF TMDS_CLK+ DIFF TMDS_CLK- DIFF DDC_CLK Chapter 2 – Hardware Information...

  • Page 38: External +12V Input (Cn14)

    Pin Name Signal Type Signal level DDC_DATA HPLG_DETECT 2.4.12 External +12V Input (CN14) Pin Name Signal Type Signal Level +121V +12V 2.4.13 DDR3L SO-DIMM Slot (CN15) Standard specification 2.4.14 LVDS Port (CN16) ※ LVDS LCD_PWR can be set to +3.3V or +5V by JP2 ※...
  • Page 39 BKL_CONTROL LCD_PWR +3.3V/+5V LVDS_A_CLK- DIFF LVDS_A_CLK+ DIFF LCD_PWR +3.3V/+5V LVDS_DA0- DIFF LVDS_DA0+ DIFF LVDS_DA1- DIFF LVDS_DA1+ DIFF LVDS_DA2- DIFF LVDS_DA2+ DIFF LVDS_DA3- DIFF LVDS_DA3+ DIFF DDC_DATA +3.3V DDC_CLK +3.3V LVDS_DB0- DIFF LVDS_DB0+ DIFF LVDS_DB1- DIFF LVDS_DB1+ DIFF Chapter 2 – Hardware Information...

  • Page 40: Com Port 1/2 & Line Out Connector (Cn17)

    LVDS_DB2- DIFF LVDS_DB2+ DIFF LVDS_DB3- DIFF LVDS_DB3+ DIFF LCD_PWR +3.3V/+5V LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF 2.4.15 COM Port 1/2 & line out connector (CN17) Pin Name Signal Type Signal Level DCDB DSRB RTSB ±9V ±9V CTSB DTRB ±9V RIB/+5V/+12V IN/ PWR +5V/+12V Chapter 2 –...

  • Page 41: Com Port2 Rs-485

    Pin Name Signal Type Signal Level DCDA DSRA RTSA ±9V ±9V CTSA DTRA ±9V AGND LOUT_R LOUT_L 2.4.16 COM port2 RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V Chapter 2 – Hardware Information...

  • Page 42: Com Port2 Rs-422

    NC/+5V/+12V +5V/+12V GNDGND 2.4.17 COM port2 RS-422 Pin Name Signal Type Signal Level ±5V RS422_TX- ±5V RS422_TX+ RS422_RX+ RS422_RX- NC/+5V/+12V +5V/+12V ※ COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. ※ COM2 RI/+5V/+12V function can be set by BOM(R248-RI/R256-+12V/R250-+5V) 2.4.18 LPC port2 (CN18) Chapter 2 –...

  • Page 43: Usb 2.0 Port 1 (Cn19)

    Pin Name Signal Type Signal Level +3.3V LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V LFRAME# +3.3V LRESET# LCLK LDRQ0 LDRQ1 +3.3V SERIRQ 2.4.19 USB 2.0 Port 1 (CN19) Chapter 2 – Hardware Information...

  • Page 44: Specifications For I/O Port

    Pin Name Signal Type Signal Level +5VSB USBD5- DIFF USBD5+ DIFF 2.4.20 Specifications for I/O Port Reference Signal Name Rate Output Digital IO Port D0~D3 +5V/(Open drain) LVDS Port Inverter / +5V/2A or +12V/2A Backlight Connector +3.3VSB +3.3V/1.1A Mini-Card Slot +1.5V +1.5V/0.375A +3.3VSB...
  • Page 45 COM Port 2 CN17 +5V/+12V +5V/1A or +12V/1A LPC Port CN18 +3.3V +3.3V/0.5A USB 2.0 Port 1 CN19 +5VSB +5VSB/0.5A Chapter 2 – Hardware Information...

  • Page 46: Function Block

    2.4.21 Function Block Chapter 2 – Hardware Information...

  • Page 47: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 48: System Test And Initialization

    4. The CMOS memory has lost power and the configuration information has been erased. The PICO-APL1 CMOS memory has an integral lithium battery backup for data retention. However, you will need to replace the complete unit when it finally runs down.

  • Page 49: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 50: Setup Submenu: Main

    Setup Submenu: Main Press “Delete” to enter Setup Options summary: (default setting) System Date Day MM:DD:YYYY Change the month, year and century. The ‘Day’ is changed automatically. System Time HH : MM : SS Change the clock of the system. Chapter 3 –...

  • Page 51: Setup Submenu: Advanced

    Setup Submenu: Advanced Options summary: (default setting) CPU Configuration CPU Configuration Parameters SATA Configuration SATA Device Configuration USB Configuration USB Configuration Parameters SIO Configuration SIO Chip configuration .Enable or Disable SIO Logical Devices, Resources and Features settings, etc. Hardware Monitor Chapter 3 –...
  • Page 52 Power Management System ACPI/Power Mode/Wake Event Configuration Digital IO Port Configuration Set Input/Output of digital Port Configuration Chapter 3 – AMI BIOS Setup...

  • Page 53: Cpu Configuration

    3.4.1 CPU configuration Options summary: C-States Disabled Enabled Optimal Default, Failsafe Default Enable/Disable C States. EIST™ Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Intel SpeedStep. Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 54: Sata Configuration

    3.4.2 SATA Configuration Options summary: Port 0/1 Disabled Enabled Optimal Default, Failsafe Default Enable/Disable SATA port Chapter 3 – AMI BIOS Setup...

  • Page 55: Hardware Monitor

    3.4.3 Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 56: Sio Configuration

    3.4.4 SIO Configuration Options summary: (default setting) Serial Port 1/2 Configuration View and Set Basic properties of the SIO Logical device. Like IO Base , IRQ Range , DMA Channel and Device Mode. Chapter 3 – AMI BIOS Setup...

  • Page 57: Serial Port Configuration

    3.4.4.1 Serial Port Configuration Options summary: Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.
  • Page 58 Options summary: DIO * Output Input Set DIO as Input or Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 59: Power Management

    3.4.6 Power Management Options summary: Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode Restore AC Power Last State Optimal Default, Failsafe Default Loss Always On Always Off RTC wake system Disable Optimal Default, Failsafe Default from S5 Fixed Time RTC wake...

  • Page 60: Setup Submenu: Chipset

    3.4.7 Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 61: North Bridge

    3.4.8 North Bridge Chapter 3 – AMI BIOS Setup...

  • Page 62: Lvds Panel Configuration

    LVDS Panel Configuration Options summary: LVDS Disabled Enabled Optimal Default, Failsafe Default Enable/Disabled this panel. LVDS Panel Type 640X480@60HZ 800X480@60HZ 800X600@60HZ 1024X600@60HZ Optimal Default, Failsafe Default 1024X768@60HZ 1280X768@60HZ 1280X800@60HZ 1280X1024@60HZ Chapter 3 – AMI BIOS Setup...
  • Page 63 1366X768@60HZ 1440X900@60HZ 1600X1200@60HZ 1920X1080@60HZ 1920X1200@60HZ Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Chapter 3 – AMI BIOS Setup...
  • Page 64 Color Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit 48-bit Select panel type Backlight Type Normal Optimal Default, Failsafe Default Inverted Select backlight control signal type Backlight Level Optimal Default, Failsafe Default 100% Select backlight control level Backlight PWM Freq 100Hz 200Hz 220Hz...

  • Page 65: South Bridge

    3.5.1 South Bridge Options summary: HD-Audio Support Disabled Enabled Optimal Default, Failsafe Default Enable/Disabled HD audio PCIe Speed Auto Optimal Default, Failsafe Default Gen1 Gen2 Configure PCIe Speed 3.5.1.1 Setup submenu: Security Chapter 3 – AMI BIOS Setup...
  • Page 66 Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.

  • Page 67: Setup Submenu: Boot

    3.5.2 Setup submenu: Boot Options summary: Quiet Boot Disabled Enabled Optimal Default, Failsafe Default EnableDisable showing boot logo. Monitor Mwait Disable Enabled Auto Optimal Default, Failsafe Default Enable/Disable Monitor Mwait. To install Linux OS, please set this item to disable. Ipv4 PXE Support Disabled Optimal Default, Failsafe Default...

  • Page 68: Setup Submenu: Exit

    Setup submenu: Exit Chapter 3 – AMI BIOS Setup...

  • Page 69: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 70: Product Cd/Dvd

    Product CD/DVD The PICO-APL1 comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers.
  • Page 71 Step 4 – Install Audio Driver Open the STEP4 - AUDIO folder and open the 0006-64bit_Win7_Win8_Win81_Win10_R279.exe file Follow the instructions Driver will be installed automatically Step 5 – Install TXE Driver Open the STEP5 - TXE folder and open the SetupTXE.exe file Follow the instructions Driver will be installed automatically Step 6 –...

  • Page 72: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 73: Watchdog Timer Registers

    Watchdog Timer Registers Table 1 : Watch dog relative IO address Default Value Note I/O Base I/O Base address for Watchdog operation. 0x2E Address This address is assigned by SIO LDN7 Table 2 : Watchdog relative register table Register Offset BitNum Value Note...

  • Page 74: Watchdog Sample Program

    A.2 Watchdog Sample Program ****************************************************************************** // WDT I/O operation relative definition (Please reference to Table 1) #define WDTAddr 0x510 // WDT I/O base address Void WDTWriteByte(byte Register, byte Value); byte WDTReadByte(byte Register); Void WDTSetReg(byte Register, byte Bit, byte Val); // Watch Dog relative definition (Please reference to Table 2) #define DevReg 0x00 // Device configuration register #define WDTRstBit 0x80 // Watchdog WDTRST# (Bit7)
  • Page 75 ******************************************************************************* // Procedure : AaeonWDTEnable VOID EnterSIOconfig IOWriteByte (IoConfAddr,0x87); IOWriteByte (IoConfAddr,0x87); VOID ExitSIOconfig IOWriteByte (IoConfAddr,0xAA); VOID SetWDT IOWriteByte (IoConfAddr,0x2B); IOWriteByte(IoConfAddr+1, (IOReadByte(IoConfAddr+1)&0xFC)); // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable(1); // Procedure : AaeonWDTConfig AaeonWDTConfig (byte Counter, BOOLEAN Unit) VOID // Disable WDT counting WDTEnableDisable( // Clear Watchdog Timeout Status WDTClearTimeoutStatus();...
  • Page 76 WDTSetBit( TimerReg, UnitBit, Unit // WDT output mode set to pulse WDTSetBit( TimerReg, ModeBit, ModeVal // WDT output mode set to active low WDTSetBit( TimerReg, PolarityBit, PolarityVal // WDT output pulse width is 25ms WDTSetBit( TimerReg, PSWidthBit, PSWidthVal // Watchdog WDTRST# Enable WDTSetBit( DevReg, WDTRstBit, WDTRstVal WDTClearTimeoutStatus()

  • Page 77: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 78: I/O Address Map

    I/O Address Map Appendix B – I/O Information...

  • Page 79: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 80: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...

  • Page 81: Appendix C - Mating Connectors

    Appendix C Appendix C – Mating Connectors...

  • Page 82: List Of Mating Connectors And Cables

    List of Mating Connectors and Cables The table notes mating connectors and available cables. Mating Mating Vendor AAEON Function Description Connector Cable Vendor QJ51191 FOXCON 16544019 HDMI 1 x HDMI -LFB4-7 2 x COMs, 1x Line-out Cable.WL125 3H-20P 712-94- 1.25mm...
  • Page 83 1 x Wafer 721-94- Box, 5P , 90D. 16553051 PINREX 05TWR Inverter DIP . ,2.0mm 1 x SATA Connector, 007-01- 16549070 SATA TechBest 180D. (M), 00757 1 x Wafer 721-81- SATA Box, 2P , 180D. 16553020 170215015 PINREX 02TW0 DIP . ,2.0mm TERMINAL.2 DT-126 Power...
  • Page 84 Housing.Dua DB9(M).Line- Jack.15cm 1 x Wafer Box, 5P , 180D. 1201-70 16559050 17000502 CATCH 0-05SM SMD. ,1.25m Board-Board Connector.80 FX18-8 16540080 P .180D(F)..Hir Hirose 0P-0.8S ose.FX18-80P -0.8SV Appendix C – Electrical Specifications for I/O Ports...

  • Page 85: Appendix D - Dio

    Appendix D Appendix D –...

  • Page 86: Dio

    The F75111 provides one serial access interface, I2C Bus, to read/write internal registers. The address of Serial Bus is 0x6E (0110_1110) The related register for configuring DIO is list as follows: Configuration and Control Register – Index 01h Power-on default [7:0] =0000_1000b Appendix D –DIO...
  • Page 87 The following is a sample code for 8 input .MODEL SMALL .CODE begin: mov cl,01h mov al,80h call CT_I2CWriteByte call Delay5ms mov al,00h mov cl,20h call CT_I2CWriteByte mov cl,22h call CT_I2CReadByte ;Input : CL - register index Appendix D –DIO...
  • Page 88 ; CH - device ID ;Output : AL - Value read Ct_I2CReadByte Proc Near mov ch,06eh mov dx, F040h + 00h ; Host Control Register xor al, al ; Clear previous commands out dx, al call Delay5ms mov dx, F040h + 04h ; Transmit Slave Address Register inc ch ;...
  • Page 89 in al, dx Ct_I2CReadByte Endp ;Input : CL - register index ; CH - device ID ; AL - Value to write ;Output: none Ct_I2CWriteByte Proc Near mov ch,06eh xchg ah, al mov dx, F040h + 00h ; Host Control Register xor al, al ;...
  • Page 90 out dx, al mov dx, F040h + 00h ; Host Control Register mov al, 12h ; Start a byte access out dx, al call CT_Chk_SMBus_Ready ;R14 Ct_I2CWriteByte Endp ; Wait until the busy bit clears, indicating that the SMBUS ; activity has concluded. CT_Chk_SMBus_Ready Proc Near mov dx, F040h + 01h ;...

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