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Aaeon PICO-APL2 User Manual

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PICO-APL2
PICO-ITX Board
st
User's Manual 1
Ed
Last Updated: January 12, 2023

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Summary of Contents for Aaeon PICO-APL2

  • Page 1 PICO-APL2 PICO-ITX Board User’s Manual 1 Last Updated: January 12, 2023...

  • Page 2: Copyright Notice

    AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ ITE is a trademark of Integrated Technology Express, Inc. ⚫ IBM, PC/AT, PS/2, and VGA are trademarks of International Business Machines ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity PICO-APL2 ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.

  • Page 7: To Prevent Damage

    If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ 连接器及线材 O：表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ/T 11363-2006 标准规定的限量要求以下。...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Function Block ......................6 Chapter 2 – Hardware Information ..................7 Dimensions ....................... 8 Jumpers and Connectors ..................9 List of Jumpers ......................10 2.3.1 Clear CMOS Jumper (JP1 Pins 1, 3, 5) ............. 10 2.3.2 Auto Power Button Enable/Disable (JP1 Pins 2, 4, 6) ......
  • Page 12 2.4.14 DDR3L SO-DIMM Slot (CN15) ..............25 2.4.15 LVDS Port (CN16) ..................26 2.4.16 COM Port 1/Port 2 and Line-Out Connector (CN17) ......27 2.4.16.1 COM Port 2 RS-485 ................28 2.4.16.2 COM Port 2 RS-422 ................29 2.4.17 LPC Port (CN18)..................30 2.4.18 USB 2.0 Port 1 (CN19) .................
  • Page 13 Setup Submenu: Security ..................54 3.6.1 Secure Boot ....................55 3.6.1.1 Key Management ................56 Setup Submenu: Boot ..................58 3.7.1 BBS Priorities ....................59 Setup Submenu: Save & Exit ................60 Chapter 4 – Drivers Installation ..................... 61 Driver Download/Installation ................62 Appendix A - I/O Information ....................

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor Pico-ITX Intel Atom® x7-E3950 (4C, 1.6GHz, up to 2GHz, TDP 12W) Intel Atom® x5-E3940 (4C, 1.6GHz, up to 1.8GHz, TDP 9.5W) Intel® Pentium® N4200 (4C, 1.1GHz, up to 2.5GHz, TDP 6W) Intel® Celeron® N3350 (2C, 1.1GHz, up to 2.4GHz, TDP 6W) Chipset Intel Atom®...
  • Page 16 Power Power Requirement +12V Power Supply Type AT/ATX Connector 2-Pin Connector Power Consumption Intel® Pentium® N4200, DDR3L 8GB, 2.16A@ +12V (Typical) Intel® Pentium® N4200, DDR3L 8GB, 2.28A@ +12V (Max) Display Controller Intel® HD Graphics 500/505 LVDS/eDP LVDS (18/24-bit 2CH) Display Interface HDMI 1.4 x 1 (2K @30Hz) (Pin header type) DDI (BIO, Optional) Multiple Display...
  • Page 17 Internal I/O USB 2.0 x 1 Serial Port COM 1: RS-232 x 1 COM 2: RS-232/422/485 x 1 (Ring/+5V/+12V) Video — SATA SATA III x 1 +5 SATA Power Connector x 1 Audio Line-Out x 1 DIO/GPIO 4-bit SMBus/I2C SMBus/I2C x 1 (SMBus as default, I2C selected by HW BOM) Touch —...
  • Page 18 Environment Operating Temperature 32°F~ 140°F (0°C ~ 60°C) Storage Temperature -40°F ~ 176°F (-40°C ~ 80°C) Operating Humidity 0% ~ 90% relative humidity, non-condensing MTBF (Hours) 525,137 CE/FCC Class A Chapter 1 – Product Specifications...

  • Page 19: Function Block

    Function Block Chapter 1 – Product Specifications...

  • Page 20: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 21: Dimensions

    Dimensions Chapter 2 – Hardware Information...

  • Page 22: Jumpers And Connectors

    Jumpers and Connectors Chapter 2 – Hardware Information...

  • Page 23: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function JP1 (Pins 1,3,5) Clear CMOS Jumper JP1 (Pins 2,4,6) Auto Power Button Enable/Disable Selection JP2 (Pins 1,3,5) LVDS Port Operating Voltage Selection JP2 (Pins 2,4,6) LVDS Port Backlight Inverter Voltage Selection...

  • Page 24: Lvds Port Operating Voltage Selection (Jp2 Pins 1,3,5)

    2.3.3 LVDS Port Operating Voltage Selection (JP2 Pins 1,3,5) +3.3V (Default) 2.3.4 LVDS Port Backlight Inverter Voltage Selection (JP2 2,4,6) +12V +5V (Default) 2.3.5 LVDS Port Backlight Lightness Control Mode (JP3) VR Mode (Default) PWM Mode Chapter 2 – Hardware Information...

  • Page 25: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Digital IO Port LVDS Port Inverter/Backlight Connector Front Panel Mini Card Slot (Half-Size) SPI Programming Header Mini Card Slot (Full-Size)/mSATA (By BOM) BIO Connector SATA Port...

  • Page 26: Digital Io Port (Cn1)

    2.4.1 Digital IO Port (CN1) Pin Name Signal Type Signal level DIO0 DIO1 DIO2 DIO3 2.4.2 LVDS Port Inverter / Backlight Connector (CN2) Pin Name Signal Type Signal level BLK_PWR +5V / +12V BKL_CONTROL Chapter 2 – Hardware Information...

  • Page 27: Front Panel (Cn3)

    Pin Name Signal Type Signal level BKL_ENABLE +3.3V Note: LVDS/BKL_PWR can be set to +5V or +12V by JP2. Note: LVDS/BKL_CONTROL can be set by JP3. Note: The driving current supports up to 2A. 2.4.3 Front Panel (CN3) Pin Name Pin Name PWR_BTN- PWR_BTN+...

  • Page 28: Mini Card Slot (Half-Sized) (Cn4)

    2.4.4 Mini Card Slot (Half-Sized) (CN4) Pin Name Signal Type Signal level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V Chapter 2 – Hardware Information...
  • Page 29 Pin Name Signal Type Signal level PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V Chapter 2 – Hardware Information...

  • Page 30: Spi Programming Header (Cn5)

    Pin Name Signal Type Signal level +3.3VSB +3.3V 2.4.5 SPI Programming Header (CN5) Pin Name Signal Type Signal level SPI_SO Signal SPI_CLK Signal +V3P3A_SPI 3.3A SPI_SI Signal SPI_CS Signal 2.4.6 Mini Card Slot (Full-Size)/mSATA (By BOM) (CN6) Pin Name Signal Type Signal level PCIE_WAKE# +3.3VSB/+3.3V...
  • Page 31 Pin Name Signal Type Signal level UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX-/mSATARX+ DIFF +3.3VSB/+3.3V +3.3V PCIE_RX+/mSATARX- DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX-/mSATATX- DIFF SMB_DATA +3.3V PCIE_TX+/mSATATX+ DIFF Chapter 2 – Hardware Information...
  • Page 32 Pin Name Signal Type Signal level USB_D- DIFF USB_D+ DIFF +3.3VSB/+3.3V +3.3V +3.3VSB/+3.3V +3.3V +1.5V +1.5V +3.3VSB/+3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 33: Bio Connector (Cn7)

    2.4.7 BIO Connector (CN7) Pin Name Pin Name +12VSB PCIE_TXN0 PCIE_RXN0 PCIE_TXP0 PCIE_RXP0 PCIE_TXN4 PCIE_RXN4 PCIE_TXP4 PCIE_RXP4 PS_ON# DDI0_DDCCLK_3P3 DDI0_DDCDATA_3P3 +5VSB +5VSB +5VSB +5VSB PCIE_REF_CLK0 RESET# PCIE_REF_CLK0# DDI0_TXN1 DDI0_TXN0 DDI0_TXP1 DDI0_TXP0 DDI0_TXN3 DDI0_TXN2 DDI0_TXP3 DDI0_TXP2 BIO_DDI0_HPD DDI0_AUXN DDI0_ AUXP USB3_TX2_N USB3_TX2_P USBN4 Chapter 2 –...
  • Page 34 Pin Name Pin Name USBP4 USB3_RX2_N USB3_RX2_P SMB_CLK SMB_DATA WAKE# USB_OC0# USB_OC1# LPC_AD0 LPC_FRAME# LPC_AD1 SERIRQ LPC_AD2 LPC_DRQ LPC_AD3 GPIO0/BIO-POWEROK AGND LPC_CLK AUD_LINEOUT_L PME# AUD_LINEOUT_R Chapter 2 – Hardware Information...

  • Page 35: Sata Port (Cn8)

    2.4.8 SATA Port (CN8) Pin Name Signal Type +V5S SATA_TX1+ DIFF SATA_TX1- DIFF SATA_RX1- DIFF SATA_RX1+ DIFF 2.4.9 Battery (CN9) Pin Name Signal Type Signal level +3.3V 3.3V Chapter 2 – Hardware Information...

  • Page 36: Usb 3.2 Gen 1 Ports 1/2 (Cn11)

    2.4.10 USB 3.2 Gen 1 Ports 1/2 (CN11) Pin Name Signal Type Signal level +5VSB USB0_D- DIFF USB0_D+ DIFF USB0_SSRX− DIFF USB0_SSRX+ DIFF USB0_SSTX− DIFF USB0_SSTX+ DIFF +5VSB USB1_D- DIFF USB1_D+ DIFF USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF Chapter 2 –...

  • Page 37: Output For Sata Hdd (Cn12)

    2.4.11 +5V Output for SATA HDD (CN12) Pin Name Signal Type Signal level 2.4.12 HDMI Port (CN13) Pin Name Signal Type Signal level TMDS_DAT1+ DIFF TMDS_DAT1- DIFF TMDS_CLK+ DIFF TMDS_CLK- DIFF DDC_DATA TMDS_DAT2+ DIFF Chapter 2 – Hardware Information...

  • Page 38: External +12V Input (Cn14)

    Pin Name Signal Type Signal level TMDS_DAT2- DIFF TMDS_DAT0+ DIFF TMDS_DAT0- DIFF DDC_CLK HPLG_DETECT 2.4.13 External +12V Input (CN14) Pin Name Signal Type Signal Level +12V +12V 2.4.14 DDR3L SO-DIMM Slot (CN15) Standard specifications. Chapter 2 – Hardware Information...

  • Page 39: Lvds Port (Cn16)

    2.4.15 LVDS Port (CN16) Pin Name Signal Type Signal Level BKL_ENABLE BKL_CONTROL LCD_PWR +3.3V/+5V LVDS_A_CLK- DIFF LVDS_A_CLK+ DIFF LCD_PWR +3.3V/+5V LVDS_DA0- DIFF LVDS_DA0+ DIFF LVDS_DA1- DIFF LVDS_DA1+ DIFF LVDS_DA2- DIFF LVDS_DA2+ DIFF LVDS_DA3- DIFF LVDS_DA3+ DIFF DDC_DATA +3.3V DDC_CLK +3.3V LVDS_DB0- DIFF LVDS_DB0+...

  • Page 40: Com Port 1/Port 2 And Line-Out Connector (Cn17)

    Pin Name Signal Type Signal Level LVDS_DB3- DIFF LVDS_DB3+ DIFF LCD_PWR +3.3V/+5V LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF Note 1: LVDS LCD_PWR can be set to +3.3V or +5V by JP2. Note 2: The max. driving current is 2A. 2.4.16 COM Port 1/Port 2 and Line-Out Connector (CN17) Pin Name Signal Type Signal Level...

  • Page 41: Com Port 2 Rs-485

    Pin Name Signal Type Signal Level RTSA CTSA DTRA AGND LOUT_R LOUT_L 2.4.16.1 COM Port 2 RS-485 Pin Name Signal Type Signal Level RS485_D- RS485_D+ NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...

  • Page 42: Com Port 2 Rs-422

    2.4.16.2 COM Port 2 RS-422 Pin Name Signal Type Signal Level ESPI_IO0 IN/OUT +1.8V ESPI_IO1 IN/OUT +1.8V ESPI_IO2 IN/OUT +1.8V ESPI_IO3 IN/OUT +1.8V +V3.3S +3.3V ESPI_CS Signal ESPI_RESET# +1.8V ESPI_CLK 1.8V Note 1: COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. Note 2: COM2 RI/+5V/+12V function can be set by BOM (R248-RI/ R256-+12V/ R250-+5V).

  • Page 43: Lpc Port (Cn18)

    2.4.17 LPC Port (CN18) Pin Name Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V +3.3V LFRAME# LRESET# +3.3V LCLK SMB_DATA +3.3V [Default]/I2C_DATA SMB_CLK +3.3V [Default]/I2C_CLK SMB_ALERT +3.3V [Default]/INT_SERIRQ Chapter 2 – Hardware Information...

  • Page 44: Usb 2.0 Port 1 (Cn19)

    2.4.18 USB 2.0 Port 1 (CN19) Pin Name Signal Type Signal Level +5VSB USBD5- DIFF USBD5+ DIFF 2.4.19 LAN (RJ-45) Port (CN20) Pin Name Signal Type MDI3+ DIFF MDI3- DIFF MDI2+ DIFF MDI2- DIFF MDI1+ DIFF MDI1- DIFF Chapter 2 – Hardware Information...

  • Page 45: Lan (Rj-45) Led Port (Cn21)

    Pin Name Signal Type MDI0+ DIFF MDI0- DIFF 2.4.20 LAN (RJ-45) LED Port (CN21) Pin Name Signal Type Signal Level +3.3V +3.3V LAN_1000# Signal LAN_ACT Signal LAN_100# Signal Chapter 2 – Hardware Information...

  • Page 46: Thermal Solutions

    Thermal Solutions Heatspreader Assembly – Part no. PICO-APL2-HSK01. Chapter 2 – Hardware Information...

  • Page 47: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 48: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or display an error message. The system can usually continue the boot up sequence with non-fatal errors.

  • Page 49: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 50: Setup Submenu: Main

    Setup Submenu: Main Options Summary System Date Day MM:DD:YYYY Change the month, year and century. The ‘Day’ is changed automatically. System Time HH : MM : SS Change the clock of the system. Chapter 3 – AMI BIOS Setup...

  • Page 51: Setup Submenu: Advanced

    Setup Submenu: Advanced Options Summary CPU Configuration Menu for CPU Configuration Parameters. SATA Configuration Menu for SATA Device Configuration. Hardware Monitor Display system hardware status (CPU temperature, etc.) SIO Configuration SIO Chip configuration. Enable or Disable SIO Logical Devices, Resources and Features settings, etc. DIO Configuration Set Input/ Output of Digital Port Configuration.

  • Page 52: Cpu Configuration

    3.4.1 CPU Configuration Options Summary C-States Disabled Enabled Optimal Default, Failsafe Default Enable/Disable C States. EIST™ Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Intel SpeedStep. Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Turbo mode. Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 53: Sata Configuration

    Options Summary Enable/Disable CPU VT-d. Power Limit 1 Enable Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Power Limit 1. 3.4.2 SATA Configuration Options Summary SATA GEN SPEED AUTO Optimal Default, Failsafe Default GEN1 GEN2 GEN3 SATA GEN SPEED selection. Port 0/ mSATA port Disabled Enabled Optimal Default, Failsafe Default...

  • Page 54: Hardware Monitor

    3.4.3 Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 55: Sio Configuration

    3.4.4 SIO Configuration Options Summary Serial Port 1/2 Configuration View and Set Basic properties of the SIO Logical device. Like IO Base, IRQ Range, DMA Channel and Device Mode. Chapter 3 – AMI BIOS Setup...

  • Page 56: Serial Port Configuration

    3.4.4.1 Serial Port Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 57: Dio Configuration

    3.4.5 DIO Configuration Options Summary DIO * Output Input Set DIO as Input or Output. Level High Optimal Default, Failsafe Default Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...

  • Page 58: Trusted Computing

    3.4.6 Trusted Computing Options Summary Security Device Disable Support Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default...
  • Page 59 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy. Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy. Endorsement Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy. TPM2.0 UEFI Spec TCG_1_2 Version...

  • Page 60: Tpm Configuration

    3.4.7 TPM Configuration Options Summary fTPM Enabled Optimal Default, Failsafe Default Disabled Enable\Disable fTPM support. Chapter 3 – AMI BIOS Setup...

  • Page 61: Power Management

    3.4.8 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode. Restore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off Determine if the system turns on or off after AC resume from G3 to S5 state. RTC wake system from Disable Optimal Default, Failsafe Default...

  • Page 62: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 63: North Bridge

    3.5.1 North Bridge Chapter 3 – AMI BIOS Setup...

  • Page 64: Lvds Panel Configuration

    3.5.1.1 LVDS Panel Configuration Options Summary LVDS Disabled Enabled Optimal Default, Failsafe Default Enable/Disabled this panel. LVDS Panel Type 640X480@60HZ 800X480@60HZ 800X600@60HZ 1024X600@60HZ 1024X768@60HZ Optimal Default, Failsafe Default 1280X768@60HZ 1280X800@60HZ 1280X1024@60HZ 1366X768@60HZ 1440X900@60HZ 1600X1200@60HZ 1920X1080@60HZ Chapter 3 – AMI BIOS Setup...
  • Page 65 Options Summary 1920X1200@60HZ Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Color Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit 48-bit Select panel depth. Backlight Type Normal Optimal Default, Failsafe Default Inverted Select backlight control signal type. Backlight Level Optimal Default, Failsafe Default 100%...

  • Page 66: South Bridge

    3.5.2 South Bridge Options Summary HD-Audio Support Disabled Enabled Optimal Default, Failsafe Default Enable/ Disabled HD audio. PCIe Speed Auto Optimal Default, Failsafe Default Gen1 Gen2 Configure PCIe Speed. LPSS I2C #2 Support Disable (D22:F1) PCI Mode Optimal Default, Failsafe Default ACPI Mode Enable/Disable LPSS I2C #2 Support.

  • Page 67: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 68: Secure Boot

    3.6.1 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 69: Key Management

    3.6.1.1 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Restore Factory Keys Force System to User Mode.
  • Page 70 Options Summary Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db). Restore DB defaults Restore DB variable to factory defaults. Platform Key (PK) Details Export Update Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures Details...

  • Page 71: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default EnableDisable showing boot logo. Monitor Mwait Disable Enabled Auto Optimal Default, Failsafe Default Enable/Disable Monitor Mwait. To install Linux OS, please set this item to disable. Ipv4 PXE Support Disabled Optimal Default, Failsafe Default Enabled...

  • Page 72: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 73: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 74: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 75: Driver Download/Installation

    Driver Download/Installation Drivers for the PICO-APL2 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/ Download the driver(s) you need and follow the steps below to install them. Step 1 – Install Chipset Driver Open the Chipset folder and open the SetupChipset.exe file...
  • Page 76 Step 4 – Install Audio Driver Open the Audio folder and open the 0006-64bit_Win7_Win8_Win81_Win10_R279.exe file Follow the instructions Driver will be installed automatically Step 5 – Install TXE Driver Open the TXE folder and open the SetupTXE.exe file Follow the instructions Driver will be installed automatically Step 6 –...

  • Page 77: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...

  • Page 78: I/O Address Map

    I/O Address Map Appendix A – I/O Information...

  • Page 79: A.2 Memory Address Map

    A.2 Memory Address Map Appendix A – I/O Information...

  • Page 80: A.3 Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A – I/O Information...

  • Page 81: Appendix B - Mating Connectors

    Appendix B Appendix B – Mating Connectors...

  • Page 82: List Of Mating Connectors And Cables

    COM Port 1, DF14-20S-1.25C COM Port 1703200153 Port 2 and 1/2 & line Line-Out out cable Connector CN18 LPC Port SHR-12V-S-B AAEON LPC 1703120130 Cable CN19 USB2.0 Port 1 Molex 51021-0500 USB Cable 1700050207 CN20 LAN (RJ-45) JST.S8B-PHDSS(LF)(S Port CN21...