Pin Configuration And Function Descriptions; Added Exposed Paddle Notation To Figure 2; Changes To Table 4 - Analog Devices AD9912 Manual

AD9912

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 5. Pin Function Descriptions
Input/
Pin No. Output
1 I
2, 4, 6, 8 I
3, 5, 7 I
9, 10, 54, 55 I/O
11, 19, 23 to 26, I
29, 30, 36, 42, 44,
45, 53
12, 13, 15, 16, 17,
18, 20, 21, 22
14, 46, 47, 49 I
27 I
28 I
31 O
DVDD_I/O 1
PIN 1
INDICATOR
DVSS 2
DVDD 3
DVSS 4
DVDD 5
DVSS 6
DVDD 7
DVSS 8
S1 9
S2 10
AVDD 11
NC 12
NC 13
AVDD3 14
NC 15
NC 16
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 2. Pin Configuration
Pin Type Mnemonic
Power DVDD_I/O
Power DVSS
Power DVDD
3.3 V CMOS S1, S2, S3, S4
Power AVDD
NC
Power AVDD3
Differential SYSCLK
input
Differential SYSCLKB
input
LOOP_FILTER
48
47
46
45
44
43
42
AD9912
41
TOP VIEW
40
(Not to Scale)
39
38
37
36
35
34
33
Description
I/O Digital Supply.
Digital Ground. Connect to ground.
Digital Supply.
Start-Up Configuration Pins. These pins are configured under program
control and do not have internal pull-up/pull-down resistors.
Analog Supply. Connect to a nominal 1.8 V supply.
No Connect. These unused pins can be left unconnected.
Analog Supply. Connect to a nominal 3.3 V supply.
System Clock Input. The system clock input has internal dc biasing and
should always be ac-coupled, except when using a crystal. Single-ended
1.8 V CMOS can also be used, but it may introduce a spur caused by an input
duty cycle that is not 50%. When using a crystal, tie the CLKMODESEL pin
to AVSS, and connect crystal directly to this pin and Pin 28.
Complementary System Clock. Complementary signal to the input
provided on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the
signal provided on Pin 27 is single-ended.
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter must be constructed and
attached to this pin. This pin should be pulled down to ground with 1 kΩ
resistor when the system clock PLL is bypassed. See Figure 46 for a diagram
of the system clock PLL loop filter.
Rev. D | Page 8 of 40
DAC_RSET
AVDD3
AVDD3
AVDD
AVDD
AVSS
AVDD
FDBK_IN
FDBK_INB
AVSS
OUT_CMOS
AVDD3
AVDD
OUT
OUTB
AVSS