Analog Devices AD9912 Manual page 29

CSB
SCLK
SDIO
Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams
Parameter Description
t Period of SCLK
CLK
t Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO)
DV
t Setup time between data and rising edge of SCLK
DS
t Hold time between data and rising edge of SCLK
DH
t Setup time between CSB and SCLK
S
t Hold time between CSB and SCLK
H
t Minimum period that SCLK should be in a logic high state
HI
t Minimum period that SCLK should be in a logic low state
LO
t
S
t
CLK
t
HIGH
t
DS
t
DH
BIT N
Figure 56. Serial Control Port Timing—Write
t
LOW
BIT N + 1
Rev. D | Page 29 of 40
AD9912
t
H