Changes To Serial Port Timing Specifications And Propagation Delay Parameters - Analog Devices AD9912 Manual

AD9912
Parameter
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
DAC OUTPUT CHARACTERISTICS
st
DCO Frequency Range (1 Nyquist Zone)
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Wideband SFDR
20.1 MHz Output
98.6 MHz Output
201.1 MHz Output
398.7 MHz Output
Narrow-Band SFDR
20.1 MHz Output
98.6 MHz Output
201.1 MHz Output
398.7 MHz Output
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/t )
CLK
SCLK Pulse Width High, t
HIGH
SCLK Pulse Width Low, t
LOW
SDO/SDIO to SCLK Setup Time, t
SDO/SDIO to SCLK Hold Time, t
SCLK Falling Edge to Valid Data on
SDIO/SDO, t
DV
CSB to SCLK Setup Time, t
S
CSB to SCLK Hold Time, t
H
CSB Minimum Pulse Width High, t
IO_UPDATE Pin Setup Time
(from SCLK Rising Edge of the Final Bit)
IO_UPDATE Pin Hold Time
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver
FDBK_IN to HSTL Output Driver with 2×
Frequency Multiplier Enabled
FDBK_IN to CMOS Output Driver
FDBK_IN Through S-Divider to CMOS
Output Driver
Frequency Tuning Word Update:
IO_UPDATE Pin Rising Edge to DAC
Output
Min Typ
0.008
45 55
5
0
50
5
20
−10
AVSS − +0.5
0.50
−79
−67
−61
−59
−95
−96
−91
−86
15
18
60
25
8
8
1.93
DS
1.9
DH
1.34
−0.4
3
PWH
t
CLK
t
CLK
2.8
7.3
8.0
8.6
60/f
S
Max Unit Test Conditions/Comments
40 MHz See Figure 28 for maximum toggle rate
65 % With 20 pF load and up to 40 MHz
6.8 ns With 20 pF load
450 MHz DAC lower limit is 0 Hz; however, the minimum slew rate
for FDBK_IN dictates the lower limit if using CMOS or HSTL
outputs
Ω Single-ended (each pin internally terminated to AVSS)
pF
31.7 mA Range depends on DAC R
+10 % FS
0.6 μA
AVSS + V Outputs connected to a transformer whose center tap is
0.50 grounded
See the Typical Performance Characteristics section
dBc 0 MHz to 500 MHz
dBc 0 MHz to 500 MHz
dBc 0 MHz to 500 MHz
dBc 0 MHz to 500 MHz
See the Typical Performance Characteristics section
dBc ±250 kHz
dBc ±250 kHz
dBc ±250 kHz
dBc ±250 kHz
µs
µs
ns Time from rising edge of RESET to high-Z on the S1, S2, S3,
S4 configuration pins
50 MHz Refer to Figure 56 for all write-related serial port parameters;
maximum SCLK rate for readback is governed by t
ns
ns
ns
ns
11 ns Refer to Figure 54
ns
ns
ns
sec t = period of SCLK in Hz
CLK
sec t = period of SCLK in Hz
CLK
ns
ns
ns S-divider bypassed
ns
ns f = system clock frequency in GHz
S
Rev. D | Page 6 of 40
resistor
SET
DV