Analog Devices AD9912 Manual page 4

AD9912
Parameter
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage
Differential Input Voltage Swing
SYSCLK PLL Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage
Differential Input Voltage Swing
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
Common-Mode Output Voltage
CMOS Output Driver
Output Voltage High (V
OH
Output Voltage Low (V
OL
Output Voltage High (V
OH
Output Voltage Low (V
OL
TOTAL POWER DISSIPATION
DDS Only
DDS with Spur Reduction On
DDS with HSTL Driver Enabled
DDS with CMOS Driver Enabled
DDS with HSTL and CMOS Drivers Enabled
DDS with SYSCLK PLL Enabled
Power-Down Mode
1
Pin 14 is in the AVDD3 group, but it is recommended that Pin 14 be tied to Pin 1.
2
AVSS = 0 V.
Min
2.4
2 0.93
632
2.4
2
0.93
632
1080
2
0.7
) 2.7
)
) 1.4
)
Typ Max Unit
1.5 pF
2.6 2.9 kΩ
1.17 1.38 V
mV p-p
3 pF
2.6 2.9 kΩ
1.17 1.38 V
mV p-p
9 100 Ω
1280 1480 mV
0.88 1.06 V
V
0.4 V
V
0.4 V
637 765 mW
686 823 mW
657 788 mW
729 875 mW
747 897 mW
648 777 mW
13 16 mW
Rev. D | Page 4 of 40
Test Conditions/Comments
System clock inputs should always be ac-
coupled (both single-ended and differential)
Single-ended, each pin
Differential
Equivalent to 316 mV swing on each leg
Single-ended, each pin
Differential
Equivalent to 316 mV swing on each leg
25 MHz, 3.2 mm × 2.5 mm AT cut
Output driver static, see Figure 27 for
output swing vs. frequency
Output driver static, see Figure 28 and
Figure 29 for output swing vs. frequency
I = 1 mA, Pin 37 = 3.3 V
OH
I = 1 mA, Pin 37 = 3.3 V
OL
I = 1 mA, Pin 37 = 1.8 V
OH
I = 1 mA, Pin 37 = 1.8 V
OL
Power-on default, except SYSCLK PLL by-
passed and CMOS driver off; SYSCLK = 1 GHz;
HSTL driver off; spur reduction off; f
200 MHz
Same as "DDS Only" case, except both spur
reduction channels on
Same as "DDS Only" case, except HSTL driver
enabled
Same as "DDS Only" case, except CMOS
driver and S-divider enabled and at 3.3 V;
CMOS f = 50 MHz (S-divider = 4)
OUT
Same as "DDS Only" case, except both HSTL
and CMOS drivers enabled; S-divider
enabled and set to 4; CMOS f
Same as "DDS Only" case, except 25 MHz on
SYCLK input and PLL multiplier = 40
Using either the power-down and enable
register or the PWRDOWN pin
=
OUT
= 50 MHz
OUT