I/O Register Map; Changes To Table 11 - Analog Devices AD9912 Manual

AD9912

I/O REGISTER MAP

All address and bit locations that are left blank in Table 12 are unused.
Table 12.
Addr
(Hex) Type 1 Name
Serial port configuration and part identification
0x0000 Serial
config.
0x0001 Reserved
0x0002 RO Part ID
0x0003 RO
0x0004 Serial
options
0x0005 AC
Power-down and reset
0x0010 Power-
down and
enable
0x0011 Reserved
0x0012 M, AC Reset
0x0013 M
System clock
0x0020 N-divider
0x0021 Reserved
0x0022 PLL
parameters
CMOS output divider (S-divider)
0x0100 Reserved
0x0101 Reserved
to
0x0103
0x0104 S-divider
and
0x0105
0x0106
Frequency tuning word
0x01A0 Reserved
to
0x01A5
FTW0
0x01A6 M
(frequency
0x01A7 M
tuning
0x01A8 M
word)
0x01A9 M
0x01AA M
0x01AB M
0x01AC M Phase
0x01AD M
Doubler and output drivers
0x0200 HSTL driver
0x0201 CMOS driver
Bit 7 Bit 6 Bit 5
SDO LSB first Soft
active (buffered) reset
PD HSTL Enable Enable
driver CMOS output
driver doubler
PD fund
DDS
VCO auto
range
Falling
edge
triggered
Rev. D | Page 30 of 40
Bit 4 Bit 3 Bit 2
Long Long Soft reset
instruction instruction
Part ID
PD
SYSCLK
PLL
S-div/2
reset
N-divider, Bits[4:0]
2× refer- VCO range
ence
S-divider, Bits[15:0]
LSB: Register 0x0104
FTW0, Bits[47:0]
LSB: Register 0x01A6
DDS phase word, Bits[7:0]
DDS phase word, Bits[13:8]
OPOL
(polarity)
Default
Bit 1 Bit 0 (Hex)
LSB first SDO 0x18
(buffered) active
0x00
0x02
0x09
Read buffer 0x00
register
Register
0x00
update
Full PD Digital PD 0xC0 or
0xD0
0x00
DDS reset 0x00
S-divider 0x00
reset
0x12
0x00
Charge pump current, 0x04
Bits[1:0]
0x30
0x00
0x00
S-divider/2 0x01
0x00
0x00
0x00
0x00
0x00
Start-up
cond.
Start-up
cond.
0x00
0x00
HSTL output doubler, 0x05
Bits[1:0]
CMOS mux 0x00