Ac Specifications; Changes To Table 2 - Analog Devices AD9912 Manual

AC SPECIFICATIONS

f = 1 GHz, DAC R = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section.
S SET
Table 2.
Parameter
FDBK_IN INPUT
Input Frequency Range
Minimum Differential Input Level
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
SYSCLK PLL Enabled
VCO Frequency Range, Low Band
VCO Frequency Range, Auto Band
VCO Frequency Range, High Band
Maximum Input Rate of System
Clock PFD
Without SYSCLK PLL Doubler
Input Frequency Range
Multiplication Range
Minimum Differential Input Level
With SYSCLK PLL Doubler
Input Frequency Range
Multiplication Range
Input Duty Cycle
Minimum Differential Input Level
Crystal Resonator with SYSCLK PLL
Enabled
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
CLOCK DRIVERS
HSTL Output Driver
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Jitter (12 kHz to 20 MHz)
HSTL Output Driver with 2× Multiplier
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Subharmonic Spur Level
Jitter (12 kHz to 20 MHz)
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Min Typ Max
10 400
225
40
250 1000
45 55
632
700 810
810 900
900 1000
100
11 200
4 66
632
6 100
8 132
50
632
10 50
100
20 725
48 52
115 165
1.5
400 725
45 55
115 165
−35
1.6
0.008 150
45 55 65
3 4.6
Rev. D | Page 5 of 40
Unit Test Conditions/Comments
Pin 40, Pin 41
MHz
mV p-p −12 dBm into 50 Ω; must be ac-coupled
V/μs
Pin 27, Pin 28
MHz Maximum f is 0.4 × f
OUT
%
mV p-p Equivalent to 316 mV swing on each leg
MHz When in the range, use the low VCO band exclusively
MHz When in the range, use the VCO auto band select
MHz When in the range, use the high VCO band exclusively
MHz
MHz
Integer multiples of 2, maximum PFD rate and system clock
frequency must be met
mV p-p Equivalent to 316 mV swing on each leg
MHz
Integer multiples of 8
% Deviating from 50% duty cycle may adversely affect
spurious performance
mV p-p Equivalent to 316 mV swing on each leg
MHz AT cut, fundamental mode resonator
Ω See the SYSCLK Inputs section for recommendations
MHz See Figure 27 for maximum toggle rate
%
ps 100 Ω termination across OUT/OUTB, 2 pF load
ps
f = 155.52 MHz, 50 MHz system clock input (see Figure
OUT
through Figure 14 for test conditions)
MHz
%
ps 100 Ω termination across OUT/OUTB, 2 pF load
dBc Without correction
ps
f = 622.08 MHz, 50 MHz system clock input (see Figure
OUT
for test conditions)
MHz See Figure 29 for maximum toggle rate; the S-divider
should be used for low frequencies because the FDBK_IN
minimum frequency is 10 MHz
% With 20 pF load and up to 150 MHz
ns With 20 pF load
AD9912
SYSCLK
12
15