Analog Devices AD9912 Manual page 37

Register 0x0503—Spur A (Continued)
Table 38.
Bits Bit Name
[7:0] Spur A phase
Register 0x0504—Spur A (Continued)
Table 39.
Bits Bit Name
[8] Spur A phase
Register 0x0505—Spur B
Table 40.
Bits Bit Name
7 HSR-B enable
6 Amplitude gain × 2
[5:4] Reserved
[3:0] Spur B harmonic
Register 0x0506—Spur B (Continued)
Table 41.
Bits Bit Name
[7:0] Spur B magnitude
Register 0x0508—Spur B (Continued)
Table 42.
Bits Bit Name
[7:0] Spur B phase
Register 0x0509—Spur B (Continued)
Table 43.
Bits Bit Name
8 Spur B phase
Description
Linear offset for Spur B phase.
Description
Linear offset for Spur A phase.
Description
Harmonic Spur Reduction B enable.
Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
Reserved.
Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate.
Description
Linear multiplier for Spur B magnitude.
Description
Linear offset for Spur B phase.
Description
Linear offset for Spur B phase.
Rev. D | Page 37 of 40
AD9912