Table of Contents
Advertisement
AXEL ULite Hardware Manual
7.1.1
Power-up sequence
The typical power-up sequence is the following:
1. (optional) PMIC_LICELL is powered by a Lithium coin cell battery
2. VIN_SOM main power supply rail is powered
3. CPU_PORn (active-low) is driven low
4. PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps
5. PMIC transitions from OFF to ON state
6. PMIC initiates power-up sequence as per I.MX6 UL requirements
7. SOM_PGOOD signal is set ti logic '1'; this active-high signal indicates
8. CPU_PORn is released.
For further details, please refer to
2
Freescale Semiconductor, PF3000 Advance Information - Power Management Integrated Circuit (PMIC) for
i.MX 7 & i.MX 6SL/SX/UL
3
Freescale Semiconductor, Data Sheet: Technical Data - i.MX 6UltraLite Applications Processors for Industrial
Products
● I.MX6 UL SNVS domain is powered (VDD_SNVS_IN)
● I.MX6 UL SNVS domain is powered (VDD_SNVS_IN)
this signal low for any reason)
that SoM's I/O is powered. This signal can be used to manage carrier
board power up sequence in order to prevent back powering (from SoM
to carrier board or vice versa). Generally speaking, all the circuitry that
interfaces SOM's I/O signals should be powered on when SOM_PGOOD
turns to logic '1'.
v.1.0.2
2
,
3
August, 2019
56/65
Advertisement
Table of Contents
