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AXEL ULite Hardware Manual
J2.21
J2.23
J2.25
J2.27
J2.29
J2.31
J2.33
J2.35
J2.37
J2.39
J2.41
J2.43
J2.45
J2.47
J2.49
J2.51
J2.53
J2.55
J2.57
J2.59
J2.61
J2.63
J2.65
J2.67
J2.69
J2.71
J2.73
J2.75
J2.77
J2.79
J2.81
J2.83
J2.85
J2.87
J2.89
J2.91
J2.93
J2.95
J2.97
ETH_TX_M
ETH_RX_P
ETH_RX_M
SNVS_TAMPER0
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER3
DGND
SNVS_TAMPER4
CSI_HSYNC
SNVS_TAMPER5
SNVS_TAMPER6
SNVS_TAMPER7
SNVS_TAMPER8
SNVS_TAMPER9
CSI_PIXCLK
CSI_MCLK
PMIC_VSNVS
DGND
VPWR
VLDO2
VLDO2
UART5_RX_DATA
UART5_TX_DATA
VLDO3
VLDO3
DGND
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_CMD
SD1_CLK
DGND
GPIO1_IO04
GPIO1_IO05
ENET2_RX_DATA1
ENET2_RX_DATA0
ENET2_TX_DATA0
v.1.0.2
LAN.TXM
LAN.RXP
LAN.RXM
CPU.SNVS_TAMPER0
CPU.SNVS_TAMPER1
CPU.SNVS_TAMPER2
CPU.SNVS_TAMPER3
DGND
CPU.SNVS_TAMPER4
CPU.CSI_HSYNC
CPU.SNVS_TAMPER5
CPU.SNVS_TAMPER6
CPU.SNVS_TAMPER7
CPU.SNVS_TAMPER8
CPU.SNVS_TAMPER9
CPU.CSI_PIXCLK
CPU.CSI_MCLK
PMIC.VSNVS
DGND
PMIC.VPWR
PMIC.VLDO2
PMIC.VLDO2
CPU.UART5_RX_DATA G13
CPU.UART5_TX_DATA
PMIC.VLDO3
PMIC.VLDO3
DGND
CPU.SD1_DATA0
CPU.SD1_DATA1
CPU.SD1_DATA2
CPU.SD1_DATA3
CPU.SD1_CMD
CPU.SD1_CLK
DGND
CPU.GPIO_IO04
CPU.GPIO_IO05
CPU.ENET2_RX_DATA1 C16
CPU.ENET2_RX_DATA0 C17
CPU.ENET2_TX_DATA0 A15
August, 2019
5
4
3
R10
R9
Internally connected to
ethernet PHY INT
P11
signal
P10
P9
F3
N8
N11
N10
N9
R6
E5
F5
34
31
15
15
F17
20
20
B3
B2
B1
A2
C2
C1
M16
M17
28/65
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