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AXEL ULite Hardware Manual
6.4.1
ENET2
The second ethernet interface requires an external PHY on the Carrier
board.
Pin Name
ENET2_RX_DATA1
ENET2_RX_DATA0
ENET2_TX_DATA0
ENET2_RX_EN
ENET2_TX_CLK
ENET2_RX_ER
ENET2_TX_EN
ENET2_TX_DATA1
ENET_MDIO
ENET_MDC
6.4.2
UART1
Pin Name
UART1_TX_DATA
UART1_RX_DATA
6.4.3
UART2 – four wires
Pin Name
UART2_TX_DATA
UART2_RX_DATA
UART2_RTS
UART2_CTS
v.1.0.2
Pin
Internal Connections
J2.93
CPU.ENET_RDATA1
J2.95
CPU.ENET_RDATA0
J2.97
CPU.ENET_TDATA0
J2.99
CPU.ENET_RXEN
J2.101
CPU.ENET_TX_CLK
J2.103
CPU.ENET_RX_ER
J2.105
CPU.ENET_TX_EN
J2.107
CPU.ENET_TDATA1
J2.127
CPU.GPIO_IO06
J2.129
CPU.GPIO_IO07
Pin
Internal Connections
J2.187
CPU.UART1_TX_DATA
J2.189
CPU.UART1_RX_DATA
Pin
Internal Connections
J2.42
CPU.UART2_TX_DATA
J2.44
CPU.UART2_RX_DATA
J2.179
CPU.UART2_RTS
J2.181
CPU.UART2_CTS
August, 2019
Ball/pin #
C16
C17
A15
B17
D17
D16
B15
A16
K17
L16
Ball/pin #
K14
K16
Ball/pin #
J17
J16
H14
J15
48/65
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