Variant Base Peripherals; Full Gpio Configuration - Dave Embedded Systems Axel ULite Hardware Manual

AXEL ULite Hardware Manual
Pin Name
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
6.2

Variant base peripherals

6.2.1

FULL GPIO configuration

The i.MX6UL GPIO module provides general-purpose pins that can be
configured as either inputs or outputs, for connections to external
devices. In addition, the GPIO peripheral can produce CORE interrupts.
The device contains 5 GPIO blocks and each GPIO block is made up to
32 identical channels. The device GPIO peripheral supports up to 124
3.3-V GPIO pins. Each channel must be properly configured, since GPIO
signals are multiplexed with other interfaces signals. For more
information on how to configure and use GPIOs, please refer to section
5.6. For additional details, please refer to chapter 26 of the i.MX6UL
APRM Rev.1.
v.1.0.2
Pin Internal Connections
J2.112 CPU.NAND_DATA04
J2.114 CPU.NAND_DATA05
J2.116 CPU.NAND_DATA06
J2.118 CPU.NAND_DATA07
August, 2019
Ball/pin #
C6
B6
A6
A5
42/65