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AXEL ULite Hardware Manual
J2.99
J2.101 ENET2_TX_CLK
J2.103 ENET2_RX_ER
J2.105 ENET2_TX_EN
J2.107 ENET2_TX_DATA1
J2.109 DGND
J2.111 N.C.
J2.113 N.C.
J2.115 N.C.
J2.117 N.C.
J2.119 N.C.
J2.121 N.C.
J2.123 N.C.
J2.125 N.C.
J2.127 GPIO1_IO06
J2.129 GPIO1_IO07
J2.131 DGND
J2.133 CSI_DATA04
J2.135 CSI_DATA05
J2.137 CSI_DATA07
J2.139 CSI_DATA06
J2.141 NVCC_ENET
J2.143 CPU_VDD_SNVS_IN CPU.VDD_SNVS_IN
J2.145 N.C.
J2.147 N.C.
ENET2_RX_EN
v.1.0.2
CPU.ENET2_RX_EN
CPU.ENET2_TX_CLK
CPU.ENET2_RX_ER
CPU.ENET2_TX_EN
CPU.ENET2_TX_DATA1 A16
DGND
CPU.GPIO_IO06
CPU.GPIO_IO07
DGND
CPU.CSI_DATA04
CPU.CSI_DATA05
CPU.CSI_DATA06
CPU.CSI_DATA07
CPU.NVCC_ENET
August, 2019
B17
D17
D16
B15
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
Internally connected to
K17
ethernet PHY (MDIO)
Internally connected to
L16
ethernet PHY (MDC)
Internally connected to
D4
NOR SPI flash
Internally connected to
D3
NOR SPI flash
Internally connected to
D2
NOR SPI flash
Internally connected to
D1
NOR SPI flash
F13
This is SoC's power rail
of the SNVS domain.
Please note that some
SOC's GPIOs belong
P12
to this power domain
Not connected. Leave
this pin floating.
Not connected. Leave
this pin floating.
29/65
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