Mitsubishi Electric MELSEC iQ-R Series User Manual page 28

Another station via co-existence network
■Access by specifying the network number and the station number, via another station on CC-
Link or C24
The following table shows the accessible route when accessing by specifying the network number and the station number via
other stations (the first route) on CC-Link or C24 from the side on which a high speed data communication module is
mounted.
: Accessible, : No combination
First access route
CC-Link
C24
*1 When the second access route is MELSECNET/H, a safety CPU cannot be accessed.
■Access to another station on CC-Link or C24 from another station on which the network
number and the station number are specified
The following table shows the accessible route when accessing other stations on CC-Link or C24 via the station (the first
route) specified by the network number and the station number from the side on which a high speed data communication
module is mounted.
: Accessible, : Not accessible
First access route
CC-Link IE Controller Network
CC-Link IE Field Network
MELSECNET/H
Ethernet (via Ethernet module)
*1 When the first access route is MELSECNET/H, a safety CPU cannot be accessed.
2 SPECIFICATIONS
26
2.2 Access Specifications for a CPU Module
Second access route
(Co-existence network)
CC-Link IE Controller Network
CC-Link IE Field Network
MELSECNET/H
Ethernet (via Ethernet module)
Second access route
(Co-existence network)
CC-Link
C24
Access target CPU module (series)
RCPU QCPU (Q mode)
Programm C Programm
able Controller able
controller module controller
CPU/ CPU/
Process Process
CPU/ CPU
Safety
CPU
*1
  
(CPU No.1 to (CPU No.1 to (CPU No.1 to
No.4) No.4) No.4)
Access target CPU module (series)
RCPU QCPU (Q mode)
Programm C Programm
able Controller able
controller module controller
CPU/ CPU/
Process Process
CPU/ CPU
Safety
CPU
*1
  
(CPU No.1 to (CPU No.1 to (CPU No.1 to
No.4) No.4) No.4)

LCPU
C Programm
Controller able
module controller
CPU
 
(Host CPU)


 
LCPU
C Programm
Controller able
module controller
CPU
 
(Host CPU)
