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Summary of Contents for ST ST7232A
- Page 1 Chipsmall Limited consists of a professional team with an average of over 10 year of expertise in the distribution of electronic components. Based in Hongkong, we have already established firm and mutual-benefit business relationships with customers from,Europe,America and south Asia,supplying obsolete and hard-to-find components to meet their specific needs.
- Page 2 ST7232A 8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE Memories ■ – 8K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In- Application Programming and In-Circuit Pro- gramming for HDFlash devices – 384 bytes RAM...
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Page 3: Table Of Contents
Table of Contents 1 INTRODUCTION ............. . 7 2 PIN DESCRIPTION . - Page 4 Table of Contents 9 I/O PORTS ..............42 INTRODUCTION .
- Page 5 Table of Contents 10.5.1 Introduction ............87 10.5.2 Main Features .
- Page 6 13.3 SOLDERING INFORMATION ..........144 14 ST7232A DEVICE CONFIGURATION AND ORDERING INFORMATION ....145 14.1 FLASH OPTION BYTES .
- Page 7 Table of Contents To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 154. 6/157...
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Page 8: Introduction
1 INTRODUCTION Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, The ST72F32A and ST7232A devices are mem- reducing power consumption when the application bers of the ST7 microcontroller family designed for is in idle or stand-by state. -
Page 9: Pin Description
ST7232A 2 PIN DESCRIPTION Figure 2. 32-Pin SDIP Package Pinout (HS) PB4 AIN0 / PD0 AIN1 / PD1 PE1 / RDI PE0 / TDO AREF OSC1 MCO / AIN8 / PF0 OSC2 BEEP / (HS) PF1 OCMP1_A / AIN10 / PF4... - Page 10 ST7232A PIN DESCRIPTION (Cont’d) Figure 4. 42-Pin SDIP and 44-Pin TQFP Package Pinouts 44 43 42 41 40 39 38 37 36 35 34 RDI / PE1 SS_1 DD_1 PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK...
- Page 11 ST7232A PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113. Legend / Abbreviations for Table Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V /0.7V...
- Page 12 ST7232A Pin n° Level Port Main function Input Output Pin Name Alternate Function (after reset) Timer B Out- PC1/OCMP1_B/ ADC Analog 24 17 9 12 I/O C Port C1 put Com- AIN13 Input 13 pare 1 25 18 10 13 PC2 (HS)/ICAP2_B...
- Page 13 ST7232A Notes: 1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
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Page 14: Register & Memory Map
ST7232A 3 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- The highest address bytes contain the user reset dressing 64K bytes of memories and I/O registers. and interrupt vectors. The available memory locations consist of 128 IMPORTANT: Memory locations marked as “Re-... - Page 15 ST7232A Table 2. Hardware Register Map Register Reset Address Block Register Name Remarks Label Status 0000h PADR Port A Data Register 0001h Port A PADDR Port A Data Direction Register 0002h PAOR Port A Option Register 0003h PBDR Port B Data Register...
- Page 16 ST7232A Register Reset Address Block Register Name Remarks Label Status 0031h TACR2 Timer A Control Register 2 0032h TACR1 Timer A Control Register 1 0033h TACSR Timer A Control/Status Register xxxx x0xxb 0034h TAIC1HR Timer A Input Capture 1 High Register...
- Page 17 ST7232A Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
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Page 18: Flash Program Memory
ST7232A 4 FLASH PROGRAM MEMORY 4.1 Introduction Depending on the overall Flash memory size in the microcontroller device, there are up to three user The ST7 dual voltage High Density Flash sectors (see Table 3). Each of these sectors can... -
Page 19: Icc Interface
Programming Tool architecture. This pin vice forces the signal. Refer to the Programming must be connected when using most ST Program- Tool documentation for recommended resistor val- ming Tools (it is used to monitor the application ues. -
Page 20: Icp (In-Circuit Programming)
ST7232A FLASH PROGRAM MEMORY (Cont’d) 4.5 ICP (In-Circuit Programming) possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP To perform ICP the microcontroller must be mode can be used to program any of the Flash... -
Page 21: Central Processing Unit
ST7232A 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION 5.3 CPU REGISTERS This CPU has a full 8-bit architecture and contains The 6 CPU registers shown in Figure 8 are not six internal registers allowing efficient 8-bit data present in the memory mapping and are accessed manipulation. - Page 22 ST7232A CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Bit 1 = Z Zero . Read/Write This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical Reset Value: 111x1xxx or data manipulation is zero.
- Page 23 ST7232A CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD in- Read/Write struction. Reset Value: 01 FFh Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, with- out indicating the stack overflow.
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Page 24: Supply, Reset And Clock Management
ST7232A 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for the frequency by two to obtain an f of 4 to 8 OSC2 securing the application in critical situations (for MHz. The PLL is enabled by option byte. If the PLL... -
Page 25: Multi-Oscillator (Mo)
ST7232A 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by the frequency ranges). In this mode of the multi- two different source types coming from the multi- oscillator, the resonator and the load capacitors oscillator block:... -
Page 26: Reset Sequence Manager (Rsm)
ST7232A 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The RESET vector fetch phase duration is 2 clock cycles. The reset sequence manager includes two RE- SET sources as shown in Figure Figure 12. RESET Sequence Phases External RESET source pulse ■...
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