ST ST7260 Series Manual
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ST ST7260 Series Manual

ST ST7260 Series Manual

Low speed usb 8-bit mcu family with up to 8k flash and serial communications interface
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Summary of Contents for ST ST7260 Series

  • Page 1 Chipsmall Limited consists of a professional team with an average of over 10 year of expertise in the distribution of electronic components. Based in Hongkong, we have already established firm and mutual-benefit business relationships with customers from,Europe,America and south Asia,supplying obsolete and hard-to-find components to meet their specific needs.
  • Page 2 Watchdog timer, 16-bit timer, USB, SCI Operating supply 4.0 V to 5.5 V CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) Operating temperature 0 °C to +70 °C Packages QFN40 (6x6) SO24 February 2009 Rev 3 1/139 www.st.com...

  • Page 3: Table Of Contents

    Contents ST7260xx Contents Description ..........7 Block diagram .
  • Page 4 ST7260xx Contents Clock system ..........27 7.3.1 General description .
  • Page 5 Contents ST7260xx 12.4 16-bit timer ..........48 12.4.1 Introduction .
  • Page 6 ST7260xx Contents 14.4.9 Endpoint n register B (EPnRB) ....... 96 14.4.10 Endpoint 0 register B (EP0RB) .
  • Page 7 Contents ST7260xx 16.6.1 RAM and hardware registers ....... . 117 16.6.2 Flash memory .

  • Page 8: Description

    ST7260xx Description Description The ST7260xx devices are members of the ST7 microcontroller family designed for USB applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash program memory.

  • Page 9: Block Diagram

    Block diagram ST7260xx Block diagram Figure 1. General block diagram INTERNAL CLOCK OSC/3 OSCIN OSCILLATOR OSCOUT OSC/4 or OSC/2 for USB PORT A PA[7:0] POWER (8 bits) SUPPLY 16-bit TIMER WATCHDOG PB[7:0] PORT B (8 bits) RESET CONTROL 8-BIT CORE PORT C USB DMA PC[2:0]...

  • Page 10: Pin Description

    ST7260xx Pin description Pin description Figure 2. 40-lead QFN package pinout PA0/MCO PA3/EXTCLK PA4/ICAP1/IT1 USBDP PA5/ICAP2/IT2 USBDM PA6/OCMP1/IT3 USBV PA7/OCMP2/IT4 (10 mA) (10 mA) OSCOUT (10 mA) OSCIN (10 mA) /IT5 (10 mA) Note: NC=Do not connect Figure 3. 24-pin SO package pinout USBVcc USBDM OSCOUT...
  • Page 11 Pin description ST7260xx RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the V is low.
  • Page 12 ST7260xx Pin description Table 2. Device pin description (QFN40) Level Port / control Main function Input Output Pin n° Pin name Alternate function (after reset) PA0/MCO Port A0 Main Clock Output Analog ground USBDP USB bidirectional data (data +) USBDM USB bidirectional data (data -) USBVCC USB power supply...
  • Page 13 Pin description ST7260xx Table 2. Device pin description (QFN40) (continued) Level Port / control Main function Input Output Pin n° Pin name Alternate function (after reset) PA3/EXTCLK Port A3 Timer External Clock PA2/ICCCLK 25 mA Port A2 ICC Clock Do not connect Do not connect Do not connect Do not connect...
  • Page 14 ST7260xx Pin description Table 3. Device pin description (SO24) Level Port / control Main function Input Output Pin n° Pin name Alternate function (after reset) Power supply voltage (4 V - 5.5 V) OSCOUT Oscillator output OSCIN Oscillator input Digital ground SCI Transmit Data PC1/TDO Port C1...

  • Page 15: Register & Memory Map

    Register & memory map ST7260xx Register & memory map As shown in Figure 4 , the MCU is capable of addressing 8 Kbytes of memories and I/O registers. The available memory locations consist of up to 384 bytes of RAM including 64 bytes of register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors.
  • Page 16 ST7260xx Register & memory map Table 4. Interrupt vector map Exit from Halt Vector address Description Masked by Remarks mode FFE0h-FFEDh Reserved area FFEEh-FFEFh Internal interrupt USB interrupt vector I- bit FFF0h-FFF1h Internal interrupt SCI interrupt vector I- bit FFF2h-FFF3h Reserved area TIMER interrupt vector I- bit...
  • Page 17 Register & memory map ST7260xx Table 5. Hardware register memory map (continued) Reset Address Block Register label Register name Remarks status 0011h TCR2 Timer Control Register 2 0012h TCR1 Timer Control Register 1 0013h TCSR Timer Control/Status Register 0014h TIC1HR Timer Input Capture High Register 1 Read only 0015h...

  • Page 18: Flash Program Memory

    ST7260xx Flash program memory Flash program memory Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external V supply.

  • Page 19: Readout Protection

    Flash program memory ST7260xx 5.3.1 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

  • Page 20: Icc Interface

    3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.

  • Page 21: Icp (In-Circuit Programming)

    Flash program memory ST7260xx ICP (in-circuit programming) To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

  • Page 22: Central Processing Unit (Cpu)

    ST7260xx Central processing unit (CPU) Central processing unit (CPU) Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. Main features 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes ●...

  • Page 23: Accumulator (A)

    Central processing unit (CPU) ST7260xx 6.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation.
  • Page 24 ST7260xx Central processing unit (CPU) Table 8. CC register description BIt Name Function Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled.

  • Page 25: Stack Pointer Register (Sp)

    Central processing unit (CPU) ST7260xx 6.3.5 Stack pointer register (SP) Reset value: 01 7Fh SP6 SP5 SP4 SP3 SP2 SP1 SP0 R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.

  • Page 26: Reset And Clock Management

    ST7260xx Reset and clock management Reset and clock management Reset The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin.

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