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Table of Contents
Related Manuals for ST ST7LITE1 B Series
Summary of Contents for ST ST7LITE1 B Series
- Page 1 Chipsmall Limited consists of a professional team with an average of over 10 year of expertise in the distribution of electronic components. Based in Hongkong, we have already established firm and mutual-benefit business relationships with customers from,Europe,America and south Asia,supplying obsolete and hard-to-find components to meet their specific needs.
- Page 2 ST7LITE1xB 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI Memories ■ – up to 4 Kbytes single voltage extended Flash (XFlash) Program memory with read-out pro- tection, In-Circuit Programming and In-Appli- SO20 cation programming (ICP and IAP). 10K write/ DIP20 erase cycles guaranteed, data retention: 20 years at 55°C.
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Page 3: Table Of Contents
Table of Contents 1 INTRODUCTION ............. . 4 2 PIN DESCRIPTION . - Page 4 Table of Contents 10.4 UNUSED I/O PINS ........... . . 52 10.5 LOW POWER MODES .
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Page 5: Introduction
ST7LITE1xB 1 INTRODUCTION The ST7LITE1xB is a member of the ST7 micro- software developers, enabling the design of highly controller family. All ST7 devices are based on a efficient and compact application code. In addition common industry-standard 8-bit core, featuring an to standard 8-bit data management, all ST7 micro- enhanced instruction set. -
Page 6: Pin Description
ST7LITE1xB 2 PIN DESCRIPTION Figure 2. 20-Pin SO and DIP Package Pinout OSC1/CLKIN/PC0 OSC2/PC1 RESET PA0 (HS)/LTIC COMPIN+/SS/AIN0/PB0 PA1 (HS)/ATIC PA2 (HS)/ATPWM0 SCK/AIN1/PB1 PA3 (HS)/ATPWM1 MISO/AIN2/PB2 PA4 (HS)/ATPWM2 MOSI/AIN3/PB3 PA5 (HS)/ATPWM3/ICCDATA COMPIN-/CLKIN/AIN4/PB4 PA6/MCO/ICCCLK/BREAK AIN5/PB5 PA7(HS)/COMPOUT AIN6/PB6 (HS) 20mA High sink capability associated external interrupt vector Figure 3. - Page 7 ST7LITE1xB PIN DESCRIPTION (Cont’d) Figure 4. 16-Pin SO and DIP Package Pinout OSC1/CLKIN/PC0 OSC2/PC1 RESET PA0 (HS)/LTIC PA2 (HS)/ATPWM0 COMPIN+/SS/AIN0/PB0 PA4 (HS)/ATPWM2 SCK/AIN1/PB1 PA5 (HS)/ATPWM3/ICCDATA MISO/AIN2/PB2 PA6/MCO/ICCCLK/BREAK MOSI/AIN3/PB3 PA7(HS)/COMPOUT COMPIN-/CLKIN/AIN4/PB4 (HS) 20mA high sink capability associated external interrupt vector 6/159...
- Page 8 ST7LITE1xB PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table Type: I = input, O = output, S = supply In/Output level: C = CMOS 0.3V /0.7V with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: –...
- Page 9 ST7LITE1xB Pin No. Level Port / Control Main Input Output Function Pin Name Alternate Function (after reset) Main Clock Output or In Circuit Communication Clock or External BREAK Caution: During normal operation this pin must be pulled- up, inter- PA6 /MCO/ nally or externally (external pull-up 12 10 10 X Port A6...
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Page 10: Register & Memory Map
ST7LITE1xB 3 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing space so the reset and interrupt vectors dressing 64K bytes of memories and I/O registers. are located in Sector 0 (F000h-FFFFh). The available memory locations consist of 128 The size of Flash Sector 0 and other device op- bytes of register locations, 256 bytes of RAM, 128 tions are configurable by Option byte (refer to... - Page 11 ST7LITE1xB Table 2. Hardware Register Map Address Block Register Label Register Name Reset Status Remarks 0000h PADR Port A Data Register 0001h Port A PADDR Port A Data Direction Register 0002h PAOR Port A Option Register 0003h PBDR Port B Data Register 0004h Port B PBDDR...
- Page 12 ST7LITE1xB Address Block Register Label Register Name Reset Status Remarks 0002Fh FLASH FCSR Flash Control/Status Register 00030h EEPROM EECSR Data EEPROM Control/Status Register 0031h SPIDR SPI Data I/O Register 0032h SPICR SPI Control Register 0033h SPICSR SPI Control Status Register 0034h ADCCSR A/D Control Status Register...
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Page 13: Flash Program Memory
ST7LITE1xB 4 FLASH PROGRAM MEMORY 4.1 Introduction 4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Commu- The ST7 single voltage extended Flash (XFlash) is nication) which allows an ST7 plugged on a print- a non-volatile memory that can be electrically ed circuit board (PCB) to communicate with an ex- erased and programmed either on a byte-by-byte ternal programming device connected via cable. -
Page 14: Icc Interface
3. The use of pin 7 of the ICC connector depends – ICCCLK: ICC output serial clock pin on the Programming Tool architecture. This pin must be connected when using most ST Program- – ICCDATA: ICC input serial data pin ming Tools (it is used to monitor the application –... -
Page 15: Memory Protection
ST7LITE1xB FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection Warning: Once set, Write/erase protection can never be removed. A write-protected flash device There are two different types of memory protec- is no longer reprogrammable. tion: Read Out Protection and Write/Erase Protec- Write/erase protection is enabled through the tion which can be applied individually. -
Page 16: Data Eeprom
ST7LITE1xB 5 DATA EEPROM 5.1 INTRODUCTION 5.2 MAIN FEATURES The Electrically Erasable Programmable Read Up to 32 Bytes programmed in the same cycle ■ Only Memory can be used as a non volatile back- EEPROM mono-voltage (charge pump) ■ up for storing data. Using the EEPROM requires a Chained erase and programming cycles ■... -
Page 17: Memory Access
ST7LITE1xB DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS the value is latched inside the 32 data latches ac- cording to its address. The Data EEPROM memory read/write access When PGM bit is set by the software, all the previ- modes are controlled by the E2LAT bit of the EEP- ous bytes written in the data latches (up to 32) are ROM Control/Status register (EECSR). - Page 18 ST7LITE1xB DATA EEPROM (Cont’d) Figure 9. Data E PROM Write Operation ⇓ Row / Byte ⇒ 30 31 Physical Address 00h...1Fh DEFINITION 20h...3Fh Nx20h...Nx20h+1Fh Read operation impossible Read operation possible Programming cycle Byte 1 Byte 2 Byte 32 PHASE 1 PHASE 2 Writing data latches Waiting E2PGM and E2LAT to fall...
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Page 19: Power Saving Modes
ST7LITE1xB DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES 5.5 ACCESS ERROR HANDLING If a read access occurs while E2LAT=1, then the Wait mode data bus will not be driven. The DATA EEPROM can enter WAIT mode on ex- If a write access occurs while E2LAT=0, then the ecution of the WFI instruction of the microcontrol- data on the bus will not be latched. -
Page 20: Register Description
ST7LITE1xB DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- Read/Write Reset Value: 0000 0000 (00h) E2LAT E2PGM Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hard- ware at the end of the programming cycle. -
Page 21: Central Processing Unit
ST7LITE1xB 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION Accumulator (A) The Accumulator is an 8-bit general purpose reg- This CPU has a full 8-bit architecture and contains ister used to hold operands and the results of the six internal registers allowing efficient 8-bit data arithmetic and logic calculations and to manipulate manipulation. - Page 22 ST7LITE1xB CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the Read/Write end of the routine. If the I bit is cleared by software Reset Value: 111x1xxx in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur-...
- Page 23 ST7LITE1xB CPU REGISTERS (Cont’d) STACK POINTER (SP) Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, with- Read/Write out indicating the stack overflow. The previously Reset Value: 01FFh stored information is then overwritten and there- fore lost.
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Page 24: Supply, Reset And Clock Management
– Auxiliary Voltage detector (AVD) with interrupt – These bytes are systematically programmed by capability for monitoring the main supply (en- ST, including on FASTROM devices. abled by option byte) Caution: If the voltage or temperature conditions change in the application, the frequency may need 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT... - Page 25 ST7LITE1xB – The x8 PLL is intended for operation with V When the PLL output signal reaches the operating the 3.3V to 5.5V range frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACC ) is reached after Refer to Section 15.1 for the option byte descrip-...
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Page 26: Register Description
ST7LITE1xB 7.3 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER RC CONTROL REGISTER (RCCR) (MCCSR) Read / Write Read / Write Reset Value: 1111 1111 (FFh) Reset Value: 0000 0000 (00h) Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad- Bits 7:2 = Reserved, must be kept cleared. justment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain...
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