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Description
Pin
1
2
3
soft reset
4
FPGA reset
5
DC/DC stop
6
BBIC reset
7
8
9
FPGA data
10
11
no use (P33)
12
no use (P34)
FPGA CLK
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PDF created with pdfFactory Pro trial version
I/O
High
A22
O
Active
A23
O
Active
O
Active
O
Normal
I
Active
O
Normal
VSS
VSS
-
TxD0
O
Active
O
Active
RxD0
I
Active
O
Fixed
(3.3V)
O
Fixed
(3.3V)
O
Active
D0
I/O
Active
D1
I/O
Active
D2
I/O
Active
D3
I/O
Active
VSS
VSS
-
D4
I/O
Active
D5
I/O
Active
D6
I/O
Active
D7
I/O
Active
D8
I/O
Active
D9
I/O
Active
D10
I/O
Active
D11
I/O
Active
D12
I/O
Active
D13
I/O
Active
D14
I/O
Active
D15
I/O
Active
VSS
VSS
-
A0
O
Active
A1
O
Active
High-
Low
Pin
Description
Z
-
Active 51
-
Active 52
-
Normal 53
-
Active 54
no use (P20)
-
Normal 55
PROGRAM
-
Active 56
FPGA DONE
-
-
57
-
Active 58
-
Active 59
-
Active 60
-
-
61
-
-
62
-
Active 63
-
Active 64
-
Active 65
-
Active 66
-
Active 67
-
-
68
-
Active 69
-
Active 70
-
Active 71
-
Active 72
-
Active 73
-
Active 74
-
Active 75
-
Active 76
-
Active 77
-
Active 78
-
Active 79
-
Active 80
-
-
81
-
Active 82
-
Active 83
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35
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I/O
High
A17
O
Active
A18
O
Active
A19
O
Active
O
Fixed
(3.3V)
FPGA
O
Normal
I
Active
MD0
I
MD1
I
FPGA INIT
I
Normal
no use
O
(WDTOVF)
MD2
I
Fixed
(3.3V)
RESETN
I
Normal
NMI
I
Fixed
(3.3V)
STBY
I
Fixed
(3.3V)
VCC
VCC
XTAL
I
EXTAL
I
Active
VSS
VSS
O
O
AS
Normal
RD
O
Normal
HWR
O
Normal
LWR
O
Normal
I
WAIT
Normal
I
IRQ1
Normal
I
IRQ0
Normal
AVCC
VCC
I
Vref
DIP SW1
I
Normal
I
DIP SW2
Normal
DIP SW3
I
Normal
DIP SW4
I
Normal
I
High-
Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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