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Pin
Description
26
27
28
29
30
31
32
33
34
35
no use (AIN2)
36
no use (A02)
37
no use (AFR2)
38
no use (ACL)
39
no use (AIN1)
40
no use (A01)
41
no use (AFR1)
42
43
44 no use (PCMIN)
45
(PCMOUT)
46
47
(PCMFR4)
48
(PCMFR3)
49
(PCMFR2)
50
(PCMFR1)
13.2. IC101 (FPGA)
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I/O
High High-
VDDPLL
VDD
-
RESETQ
I
Active
DUP
O
Active
DDN
I
Active
DCL
I
Active
FSC
I
Active
VSS
VSS
-
VDD
VDD
-
VDD5
-
VDD5
I
-
O
-
O
-
O
-
I
-
O
-
O
-
VSS
VSS
-
VDD
VDD
-
I
-
no use
O
-
no use
O
-
(PCMCL)
no use
O
-
no use
O
-
no use
O
-
no use
O
-
Low Pin
Description
Z
-
-
76
RXDSG
-
Normal 77 no use (RXOFF)
-
Active 78
RXDA
-
Active 79
TXDA
-
Active 80
PAON
-
Normal 81
-
-
82
-
-
83 no use (ADPFR)
-
-
84 no use (ADPCL)
-
-
85
no use
(ADPOUT)
-
-
86 no use (ADPIN)
-
-
87
IOMCLK
-
-
88
no use
(MPCLK)
-
-
89 no use (CLK10)
-
-
90
VDD5
-
-
91
-
-
92
-
-
93
-
-
94
-
-
95
-
-
96
-
-
97
-
-
98
-
-
99
-
-
100
31
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I/O
High
O
Active
O
-
I
Active
O
Active
O
Normal
VDD
VDD
-
VSS
VSS
-
O
-
O
-
O
-
I
-
I
-
O
-
O
-
-
VDD5
VDD
VDD
-
VSS
VSS
-
AD7
I/O
Active
AD6
I/O
Active
AD5
I/O
Active
AD4
I/O
Active
AD3
I/O
Active
AD2
I/O
Active
AD1
I/O
Active
AD0
I/O
Active
High-
Low
Z
-
Normal
-
Normal
-
-
Active
-
Active
-
-
-
-
-
-
-
Fixed
-
-
-
-
-
-
Active
-
Active
-
Active
-
Active
-
Active
-
Active
-
Active
-
Active
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