Panasonic KX-TDA0142CE Service Manual page 26

signal and 4MHz clock) and digital data in ST-BUS format from the analog signal provided by
PBX.
These clocks and digital data is transferred to FPGA (IC101) and HDLC control IC (IC112). HDLC
means High Level Data Line Control, a protocol for highly reliable data communication.
This ST-BUS digital data contains data channel, control channel and voice channel.
The first 2bits of the data channel is the control data. The control data is transferred to HDLC IC
and buffered in it. When the size of buffered data reaches certain value, HDLC IC interrupts to
the CPU. Then the CPU reads the control data from HDLC IC.
Voice channel contains 4 ADPCM data. And superframe synchronization signal is carried by HK
bit of control channel.
4 ADPCM data and superframe synchronization signal is transferred to FPGA (IC101).
Note:
The GND of CS(KX-TDA0142) is not common to the GND of the PBX itself, care must be taken
when using a measuring device such as an oscilloscope.(Make sure to use the measuring
device with its frame ground open.)
12.4. FPGA
FPGA (IC101) has the following features.
(1) ST-BUS I/F,IOM-2 I/F
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