Sdio Interface - Quectel FC21 Hardware Design

3.5.1.3. SDIO Interface

The following table shows the pin definition of SDIO interface.
Table 8: Pin Definition of SDIO Interface
Pin Name Pin No.
SDIO_D3 22
SDIO_D2 23
SDIO_D1 24
SDIO_D0 25
SDIO_CLK 26
SDIO_CMD 27
The following figure shows the SDIO interface connection between FC21 and EC2x&EG2x-G.
FC21
SDIO_CLK
SDIO_CMD
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
In order to ensure the performance of SDIO, please comply with the following principles:
 SDIO signals are very high-speed signals. Please prevent crosstalk among them and other sensitive
signals.
 Keep SDIO traces as parallel as possible in the same layer. Make sure SDIO lines are guarded by
ground vias and not crossed.
FC21_Hardware_Design
I/O Description
IO SDIO data bus D3
IO SDIO data bus D2
IO SDIO data bus D1
IO SDIO data bus D0
DI SDIO bus clock
IO SDIO bus command
VIO
VIO
VIO
Figure 6: SDIO Interface Connection
Wi-Fi&BT Module Series
FC21 Hardware Design
Comment
1.8V power domain.
1.8V power domain.
Require external pull-up to 1.8V.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
VIO
VIO
EC2x&EG2x-G
SD1_CLK
SD1_CMD
SD1_D0
SD1_D1
SD1_D2
SD1_D3
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