Quectel FC21 Hardware Design page 19

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LTE_UART_
6
RXD
RF Interface
Pin Name
Pin No.
RF_ANT
30
Other Interfaces
Pin Name
Pin No.
DBG_TXD
4
2)
32KHz_IN
19
RESERVED Pins
Pin Name
Pin No.
2, 3,
33~35,
RESERVED
37, 41,
42, 47
NOTES
1)
1.
indicates that SDIO_D2 is a boot strap signal, which must be kept at high level for normal
operation during power on.
2)
2.
indicates that 32KHz_IN is reserved on FC21 module since the sleep function is still to be
developed.
FC21_Hardware_Design
LTE/Wi-Fi&BT
DI
coexistence signal
I/O
Description
Wi-Fi/BT antenna
IO
interface
I/O
Description
Used for software
OD
debugging
Low power.
DI
External 32.768kHz
clock input.
I/O
Description
Reserved
Wi-Fi&BT Module Series
FC21 Hardware Design
pin open.
V
min=-0.3V
IL
1.8V power domain.
V
max=0.54V
IL
If unused, keep this
V
min=1.26V
IH
pin open.
V
max=2.0V
IH
DC Characteristics
Comment
50Ω impedance.
DC Characteristics
Comment
1.8V power domain.
Require external pull-
V
max=0.18V
OL
up to 1.8V.
V
min=1.62V
OH
If unused, keep this pin
open.
V
min=-0.3V
IL
1.8V power domain.
V
max=0.54V
IL
If unused, keep this pin
V
min=1.26V
IH
open.
V
max=2.0V
IH
DC Characteristics
Comment
Keep these pins
open.
18 / 52

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