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Quectel QuecOpen BG952A-GL Hardware Design

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BG952A-GL
Hardware Design
LPWA Module Series
Version: 1.0.0
Date: 2022-04-30
Status: Preliminary
QuecOpen
www.quectel.com

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Summary of Contents for Quectel QuecOpen BG952A-GL

  • Page 1 BG952A-GL QuecOpen Hardware Design LPWA Module Series Version: 1.0.0 Date: 2022-04-30 Status: Preliminary www.quectel.com...
  • Page 2 To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable.
  • Page 3 Copyright © Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved. Hereby, [Quectel Wireless Solutions Co., Ltd.] declares that the radio equipment type [BG952A-GL] is in compliance with Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address: http://www.quectel.com...

  • Page 4: Safety Information

    Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.
  • Page 5 LPWA Module Series metal powders. BG952A-GL_QuecOpen_Hardware_Design 4 / 72...

  • Page 6: About The Document

    LPWA Module Series About the Document Revision History Version Date Author Description Arvin WU/ 2022-04-30 Creation of the document Ben JIANG Arvin WU/ 1.0.0 2022-04-30 Preliminary Ben JIANG BG952A-GL_QuecOpen_Hardware_Design 5 / 72...

  • Page 7: Table Of Contents

    LPWA Module Series Contents Safety Information ............................3 About the Document ............................ 5 Contents .................................6 Table Index ..............................8 Figure Index ..............................10 Introduction ............................11 1.1. Special Mark ..........................11 Product Concept ..........................12 General Description ........................12 2.1. 2.2. Key Features ..........................13 2.3.
  • Page 8 LPWA Module Series 3.18. STATUS .............................44 3.19. GRFC Interfaces* ........................45 GNSS Receiver ............................ 46 4.1. General Description ........................46 4.2. GNSS Performance ........................46 4.3. Layout Guidelines ........................47 Antenna Interfaces ..........................48 5.1. Main Antenna Interface ......................48 5.1.1. Pin Definition ........................
  • Page 9 LPWA Module Series Table Index Table 1: Special Mark ...........................11 Table 2: Frequency Bands and GNSS Types of BG952A-GL QuecOpen ..........12 Table 3: Key Features of BG952A-GL QuecOpen ..................13 Table 4: Definition of I/O Parameters ......................19 Table 5: Pin Description ..........................
  • Page 10 LPWA Module Series Table 42: Terms and Abbreviations ......................71 BG952A-GL_QuecOpen_Hardware_Design 9 / 72...
  • Page 11 LPWA Module Series Figure Index Figure 1: Functional Diagram of BG952A-GL ..................... 15 Figure 2: Pin Assignment (Top View) ......................18 Figure 3: Power Supply Limits during Burst Transmission ................. 28 Figure 4: Star Structure of the Power Supply ..................... 29 Figure 5: Auto Power-on Circuit ........................30 Figure 6: Turn on the Module with a Driving Circuit...

  • Page 12: Introduction

    LPWA Module Series Introduction QuecOpen is an application solution where the module acts as a main processor. With the development ® of communication technology and the ever-changing market demands, more and more customers have realized the advantages of QuecOpen solution, especially the advantage in reducing product cost. With ®...

  • Page 13: Product Concept

    LPWA Module Series Product Concept 2.1. General Description As an embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module, it provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides GNSS function to meet your specific application demands. The module is based on an architecture in which WWAN (LTE) and GNSS Rx chains share certain hardware blocks.

  • Page 14: Key Features

    LPWA Module Series pins. With a compact profile of 23.6 mm × 19.9 mm × 2.2 mm, it can meet almost all requirements for M2M applications such as security, smart metering, tracking system, and wireless POS. 2.2. Key Features Table 3: Key Features of BG952A-GL QuecOpen Features Details Supply voltage: 2.2–4.35...
  • Page 15  GNSS GPS, GLONASS  3GPP TS 27.007 and 3GPP TS 27.005 AT commands  AT Commands Quectel enhanced AT commands  Network Indication One NET_STATUS pin for network connectivity status indication Main antenna interface (ANT_MAIN)  Antenna Interfaces GNSS antenna interface (ANT_GNSS) ...

  • Page 16: Functional Diagram

    LPWA Module Series When the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/μs. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 ms.

  • Page 17: Evaluation Board

    LPWA Module Series 2.4. Evaluation Board To facilitate application design with the module conveniently, Quectel supplies the evaluation board (LTE OPEN EVB), a USB to RS-232 converter cable, a micro-USB cable, an earphone, antennas and other peripherals to control or test the module. For more details, see document [2].

  • Page 18: Application Interfaces

    LPWA Module Series Application Interfaces 3.1. General Description BG952A-GL QuecOpen is equipped with 102 LGA pins. The subsequent chapters provide detailed descriptions of the following interfaces: Power supply  PON_TRIG interface  (U)SIM interface  USB interface  UART interfaces ...

  • Page 19: Pin Assignment

    LPWA Module Series 3.2. Pin Assignment The following figure shows the pin assignment of the module. Figure 2: Pin Assignment (Top View) BG952A-GL_QuecOpen_Hardware_Design 18 / 72...

  • Page 20: Pin Description

    LPWA Module Series  NOTES ADC input voltage must not exceed 1.8 V. Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. On BG952A-GL, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module.
  • Page 21 LPWA Module Series Table 5: Pin Description Power Supply Pin Name Pin No. Description DC Characteristics Comment Power supply for VBAT_BB the module’s See NOTE 1. Vmax = 4.35 V baseband part Vmin = 2.2 V Power supply for Vnom = 3.3 V VBAT_RF the module’s RF See NOTE 1...
  • Page 22 LPWA Module Series min = -0.2 V 1.8 V power Used to wake up max = 0.3 V domain. PON_TRIG* the MCU in low min = 1 V If unused, keep power mode max = 1.98 V these pins open. Interface* Pin Name Pin No.
  • Page 23 LPWA Module Series Main UART Can be configured MAIN_TXD transmit as GPIOs. max = 0.36 V DTE clear to send min = 1.44 V signal from DCE MAIN_CTS (Connect to DTE’s CTS) DTE request to min = -0.2 V send signal from max = 0.54 V MAIN_RTS DCE (Connect to...
  • Page 24 LPWA Module Series General-purpose Voltage range: If unused, keep ADC1 ADC interface 0.1–1.8 V these pins open. Can be configured General-purpose Voltage range: ADC0 as GPIOs. ADC interface 0.1–1.8 V Other Interfaces Pin Name Pin No. Description DC Characteristics Comment 1.8 V power domain.
  • Page 25 LPWA Module Series LNA power supply RESERVED Pins Pin Name Pin No. Description DC Characteristics Comment Keep these pins RESERVED 11–14, 16, 52,53, 56,57, 63, 75–78, 92,93,97,98 open. GPIO Interfaces Pin Name Pin No. Description DC Characteristics Comment GPIO1 GPIO2 GPIO3 GPIO4 GPIO5...

  • Page 26: Pins Multiplexing

    LPWA Module Series NOTES When the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/μs. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 2.

  • Page 27: Recovery Mode

    LPWA Module Series The module remains the ability to receive paging message, SMS and TCP/UDP data Sleep Mode from the network normally. In this mode, the current consumption is reduced to a low level. The module’s power supply is shut down by its power management unit. In this mode, Power OFF the software is inactive, the serial interfaces are inaccessible, while the operating Mode...

  • Page 28: Power Saving Mode

    LPWA Module Series Upgrade firmware via CLI UART interface. NOTE 1. In recovery mode, pin 25 functions as CLI_RTS and pin 26 functions as CLI_CTS, while in other modes they are GPIO pins. 2. Since the baud rate of the serial port required to download firmware to the baseband chip is 3 Mbps, the flow control pins of the CLI serial port need to be reserved.

  • Page 29: Power Supply

    LPWA Module Series 3.7. Power Supply 3.7.1. Power Supply Pins The module provides two VBAT pins for connection with an external power supply. The following table shows the details of VBAT_BB and VBAT_RF pins and ground pins. Table 9: Power Supply Pin Definition Pin Name Pin No.

  • Page 30: Power Supply Monitoring

    LPWA Module Series recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 0.6 mm, and the width of VBAT_RF trace should be no less than 2 mm.
  • Page 31 LPWA Module Series Table 10: PWRKEY Pin Definition Pin Name Pin No. Description Comment Turn on/off Internally pulled up with a 470 kΩ PWRKEY module resistor. When the module is in power-off mode, it can be turned on by driving PWRKEY low for 500–1000 ms. It is recommended to use an auto power-on circuit to control PWRKEY, as shown below.
  • Page 32 LPWA Module Series Figure 6: Turn on the Module with a Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the button, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection.

  • Page 33: Turn Off Module

    LPWA Module Series Figure 8: Power-up Timing NOTES Ensure that VBAT is stable before pulling down PWRKEY and keep the interval no less than 100 ms. 3.8.2. Turn off Module After the module is turned off or enters PSM, do not pull up any I/O pin of the module. Otherwise, the module will have additional power consumption and may have damaged pins.

  • Page 34: Reset The Module

    LPWA Module Series Figure 9: Power-down Timing (PWRKEY) 3.9. Reset the Module The module can be reset by driving RESET_N low for at least 100 ms and then releasing it. The RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground.
  • Page 35 LPWA Module Series Figure 10: Reference Circuit of RESET_N with a Driving Circuit Another way to control the RESET_N is by using a button directly. Figure 11: Reference Circuit of RESET_N with a Button The reset scenario is illustrated in the following figure. Figure 12: Reset Timing BG952A-GL_QuecOpen_Hardware_Design 34 / 72...

  • Page 36: Pon_Trig Interface

    LPWA Module Series NOTE Make sure that there is no large capacitance on RESET_N. 3.10. PON_TRIG Interface BG952A-GL QuecOpen provides one PON_TRIG pin. Drive PON_TRIG is used to wake up the internal MCU. PON_TRIG is not pulled up/down internally by default. Table 12: Pin Definition of PON_TRIG Interface Pin Name Pin No.

  • Page 37: U)Sim Interface

    LPWA Module Series 3.11. (U)SIM Interface The module supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 13: Pin Definition of (U)SIM Interface Pin Name Description Comment USIM_DET (U)SIM card hot-plug detect 1.8 V power domain. Only 1.8 V (U)SIM card is USIM_VDD (U)SIM card power supply...
  • Page 38 LPWA Module Series If (U)SIM card detection function is not needed, keep USIM_DET unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 15: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in (U)SIM circuit design: Keep the placement of (U)SIM card connector as close to the module as possible.

  • Page 39: Usb Interface

    LPWA Module Series 3.12. USB Interface* BG952A-GL QuecOpen provides one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports full speed mode only. The following table shows the pin definition of USB interface. Table 14: Pin Definition of USB Interface Pin Name Pin No.

  • Page 40: Uart Interfaces

    LPWA Module Series Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is  important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. Junction capacitance of the ESD protection device might cause influences on USB data lines, so pay ...
  • Page 41 LPWA Module Series MAIN_RI* Main UART ring indication Table 16: Pin Definition of CLI UART Interface Pin Name Pin No. Description Comment 1.8 V power domain. CLI_TXD2 CLI UART2 transmission If unused, keep them CLI_RXD2 CLI UART2 reception open. 1.8 V power domain. CLI_TXD1 CLI UART1 transmission If unused, keep them...

  • Page 42: I2C Interface

    LPWA Module Series Figure 18: Main UART Reference Design (Transistor Circuit) NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. The UART interface should be disconnected in PSM and power off modes. Otherwise, the module will have additional power consumption and may have damaged pins.

  • Page 43: Spi Interfaces

    LPWA Module Series Figure 19: Reference Design of I2C Interface with an External I2C Interface Sensor 3.15. SPI Interfaces* The module provides three SPI interfaces. 2 SPI interfaces for master mode, 1 SPI interface for slave mode. The SPI interfaces function is multiplexed from GPIOs. SPIM0 and SPIM1 interfaces in master mode up to 25 MHz.

  • Page 44: Network Status Indication

    LPWA Module Series If unused, keep these ADC0 General-purpose ADC interface pins open. Can be ADC1 General-purpose ADC interface configured as GPIOs. The following table describes characteristics of ADC interfaces. Table 18: Characteristics of ADC Interfaces Parameter Min. Typ. Max. Unit Voltage Range Resolution...

  • Page 45: Status

    LPWA Module Series Table 20: Operating Status of NET_STATUS Pin Name Indicator Status (Logic Level Changes) Network Status Flicker slowly (200 ms High/1800 ms Low) Network searching Flicker slowly (1800 ms High/200 ms Low) Idle NET_STATUS Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always High Voice calling...

  • Page 46: Grfc Interfaces

    LPWA Module Series Figure 21: Reference Design of STATUS 3.19. GRFC Interfaces* The module provides two generic RF control interfaces for the control of external antenna tuners. Table 22: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comment GRFC1 Generic RF controller 1.8 V power domain.

  • Page 47: Gnss Receiver

    LPWA Module Series GNSS Receiver 4.1. General Description BG952A-GL QuecOpen supports GPS and GLONASS satellite systems using dedicated hardware accelerators in a power and cost-efficient manner. The module supports standard NMEA-0183 protocol, and outputs GNSS NMEA sentences at 1 Hz data update rate via CLI UART interface by default.

  • Page 48: Layout Guidelines

    LPWA Module Series XTRA enabled Accuracy (GNSS) CEP-50 Autonomous @ open sky 1.41 NOTES Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.

  • Page 49: Antenna Interfaces

    LPWA Module Series Antenna Interfaces The module includes a main antenna interface and a GNSS antenna interface. The impedance of antenna ports is 50 Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of the main antenna interface is shown below. Table 25: Pin Definition of the Main Antenna Interface Pin Name Pin No.

  • Page 50: Reference Design

    LPWA Module Series LTE HD-FDD B13 777–787 746–756 LTE HD-FDD B17 704–716 734–746 LTE HD-FDD B18 815–830 860–875 LTE HD-FDD B19 830–845 875–890 LTE HD-FDD B20 832–862 791–821 LTE HD-FDD B25 1850–1915 1930–1995 LTE HD-FDD B26 814–849 859–894 LTE HD-FDD B27 807–824 852–869 LTE HD-FDD B28...

  • Page 51: Gnss Antenna Interface

    LPWA Module Series 5.2. GNSS Antenna Interface 5.2.1. Pin Definition Table 27: Pin Definition of GNSS Antenna Interface Pin Name Pin No. Description Comment ANT_GNSS GNSS antenna interface 50 Ω impedance 5.2.2. GNSS Operating Frequency Table 28: GNSS Operating Frequency Type Frequency Unit...

  • Page 52: Reference Design Of Rf Layout

    LPWA Module Series 5.3. Reference Design of RF Layout For users’ PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the spacing between RF traces and...
  • Page 53 LPWA Module Series Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to ...

  • Page 54: Antenna Installation

    LPWA Module Series For more details about RF layout, see document [6]. 5.4. Antenna Installation 5.4.1. Antenna Requirements Table 29: Antenna Requirements Antenna Type Requirements Frequency range: 1559–1609 MHz Polarization: RHCP or linear GNSS VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi VSWR: ≤...
  • Page 55 LPWA Module Series Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 29: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connectors. Figure 30: Space Factor of Mated Connectors (Unit: mm) BG952A-GL_QuecOpen_Hardware_Design 54 / 72...
  • Page 56 LPWA Module Series For more details, visit http://www.hirose.com. BG952A-GL_QuecOpen_Hardware_Design 55 / 72...

  • Page 57: Reliability, Radio And Electrical Characteristics

    LPWA Module Series Reliability, Radio and Electrical Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter Min.

  • Page 58: Operating And Storage Temperatures

    LPWA Module Series 6.3. Operating and Storage Temperatures Table 32: Operating and Storage Temperatures Parameter Min. Typ. Max. Unit Operating Temperature Range + 25 + 75 ºC Extended Temperature Range + 85 ºC Storage Temperature Range + 90 °C NOTES Within the operating temperature range, the module meets 3GPP specifications.
  • Page 59 LPWA Module Series LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 Idle State...
  • Page 60 LPWA Module Series LTE HD-FDD B66 @ 23.19 dBm LTE HD-FDD B1 @ 22.7 dBm LTE HD-FDD B2 @ 22.72 dBm LTE HD-FDD B3 @ 23.24 dBm LTE HD-FDD B4 @ 23.19 dBm LTE HD-FDD B5 @ 23.32 dBm LTE HD-FDD B8 @ 22.71 dBm LTE HD-FDD B12 @ 22.8 dBm LTE Cat NB1 data transfer LTE HD-FDD B13 @ 23.23 dBm...

  • Page 61: Tx Power

    LPWA Module Series 6.5. Tx Power Table 35: Tx Power Frequency Bands Max. Tx Power Min. Tx Power LTE HD-FDD: B1/B2/B3/B4/B5/B8/B12/B13/B17 /B18/ 23 dBm ±2.7 dB < -39 dBm B19/B20/B25/B26 /B27 /B28/B66 6.6. RF Receiving Sensitivity Table 36: Conducted RF Receiving Sensitivity of BG952A-GL QuecOpen Receiving Sensitivity (dBm) Frequency Band Primary...

  • Page 62: Esd

    LPWA Module Series LTE HD-FDD B19 -107/-102.3 -115.3/-107.5 LTE HD-FDD B20 -106.6/-99.8 -114.6/-107.5 LTE HD-FDD B25 -106.4/-100.3 -114.3/-107.5 LTE HD-FDD B26 -107/-100.3 LTE HD-FDD B27 -107.2/-100.8 LTE HD-FDD B28 -106.6/-100.8 -114.6/-107.5 LTE HD-FDD B66 -106.8/-101.8 -114.9/-107.5 6.7. ESD If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent.

  • Page 63: Mechanical Dimensions

    LPWA Module Series Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions Figure 31: Module Top and Side Dimensions BG952A-GL_QuecOpen_Hardware_Design 62 / 72...
  • Page 64 LPWA Module Series 19.90±0.20 1.00 1.10 0.55 1.95 1.10 0.25 1.00 Pin 1 5.10 0.25 1.00 0.85 1.70 1.90 1.10 1.00 1.70 0.70 1.00 1.70 0.50 0.25 0.55 0.25 1.10 40x1.0 62x0.7 62x1.10 40x1.0 Figure 32: Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard.

  • Page 65: Recommended Footprint

    LPWA Module Series 7.2. Recommended Footprint 19.90±0.20 9.95 9.95 9.15 9.15 7.45 7.15 1.95 1.00 0.25 1.10 1.10 0.55 1.00 0.25 Pin 1 2.50 1.70 1.70 1.10 1.70 0.85 0.15 0.85 1.70 0.25 1.70 2.55 0.85 1.00 1.10 1.00 0.70 1.10 2.50 1.10...

  • Page 66: Top And Bottom Views

    7.3. Top and Bottom Views Figure 34: Top and Bottom Views NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. BG952A-GL_QuecOpen_Hardware_Design 65 / 72...

  • Page 67: Storage, Manufacturing And Packaging

    LPWA Module Series Storage, Manufacturing and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %.

  • Page 68: Manufacturing And Soldering

    LPWA Module Series NOTES This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed.

  • Page 69: Packaging

    Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. Due to the SMT process complexity, please contact Quectel Technical Support in advance regarding any situation that you are not sure about, or any process (e.g., selective soldering, ultrasonic soldering) that is not mentioned in document [6].

  • Page 70: Plastic Reel

    LPWA Module Series Figure 36: Carrier Tape Dimension Drawing Table 39: Carrier Tape Dimension Table (Unit: mm) 0.35 20.2 3.15 6.65 20.2 1.75 8.3.2. Plastic Reel Figure 37: Plastic Reel Dimension Drawing Table 40: Plastic Reel Dimension Table (Unit: mm) øD1 øD2 BG952A-GL_QuecOpen_Hardware_Design...

  • Page 71: Packing Process

    LPWA Module Series 44.5 8.3.3. Packing Process Place the module onto the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape on the plastic reel and use the protective tape for protection. One plastic reel can load 250 modules. Place the packaged plastic reel, humidity indicator card and desiccant bag inside a vacuum bag, then vacuumize it.

  • Page 72: Appendix A References

    LPWA Module Series Appendix A References Table 41: Related Documents Document Name Quectel_BG770A-GL&BG95xA-GL_GNSS_Application_Note Quectel_LTE_OPEN_EVB_User_Guide Quectel_BG77xA-GL&BG95xA-GL_AT_Commands_Manual Quectel_BG77xA-GL&BG95xA-GL_QCFG_AT_Commands_Manual Quectel_RF_Layout_Application_Note Quectel_Module_Secondary_SMT_Application_Note Quectel_BG952A-GL_QuecOpen_GPIO_Configuration Quectel_BG950A-GL&BG951A-GL_TE-A_User_Guide Table 42: Terms and Abbreviations Abbreviation Description Analog-to-Digital Converter Bits Per Second CHAP Challenge Handshake Authentication Protocol Coding Scheme DFOTA Delta Firmware Upgrade Over The Air Downlink e-I-DRX...
  • Page 73 LPWA Module Series EGPRS Enhanced General Packet Radio Service EGSM Extended GSM (Global System for Mobile Communications) Evolved Packet Core Electrostatic Discharge Frequency Division Duplex GMSK Gaussian Minimum Shift Keying Global System for Mobile Communications Home Subscriber Server Inter-Integrated Circuit Light Emitting Diode Low Noise Amplifier Long Term Evolution...
  • Page 74 LPWA Module Series Serial Peripheral Interface Time-Division Multiplexing Transient Voltage Suppressor Uplink User Equipment Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value...
  • Page 75 The minimum distance between the user and/or any bystander and the radiating structure of the transmitter is 20cm. Hereby, We, Quectel Wireless Solutions Co., Ltd. declares that the radio equipment type BG951A-GL is in compliance with the Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address: Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District,...
  • Page 76 LPWA Module Series ❒ NB LTE Band2/25:≤11.000dBi ❒ NB LTE Band4/66:≤8.000dBi ❒ NB LTE Band5:≤12.541 dBi ❒ NB LTE Band12:≤11.798dBi ❒ NB LTE Band13:≤12.214dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
  • Page 77 LPWA Module Series The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
  • Page 78 LPWA Module Series and must not transmit simultaneously with any other antenna or transmitter. L'autre utilisé pour l'émetteur doit être installé pour fournir une distance de séparation d'au moins 20 cm de toutes les personnes et ne doit pas être colocalisé ou fonctionner conjointement avec une autre antenne ou un autre émetteur.
  • Page 79 LPWA Module Series “Contains IC: 10224A-022BG952AGL” or “where: 10224A-022BG952AGL is the module’s certification number”. Le produit hôte doit être correctement étiqueté pour identifier les modules dans le produit hôte. L'étiquette de certification d'Innovation, Sciences et Développement économique Canada d'un module doit être clairement visible en tout temps lorsqu'il est installédans le produit hôte;...
  • Page 80 LPWA Module Series BG952A-GL_QuecOpen_Hardware_Design 79 / 72...

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